Lioncash
d5461be6b4
A64: Implement SM3SS1
2020-04-22 20:46:16 +01:00
Lioncash
2db032ac83
A64: Implement SRI (vector)
2020-04-22 20:46:16 +01:00
Lioncash
11005cfe26
A64: Implement SLI (vector)
2020-04-22 20:46:16 +01:00
Lioncash
e3d9bf55e7
A64: Implement SRSRA (vector)
2020-04-22 20:46:16 +01:00
Lioncash
bc6016cad7
A64: Implement SRSHR (vector)
2020-04-22 20:46:16 +01:00
Lioncash
a2f8cdf0a3
A64: Implement SSUBL/SSUBL2
2020-04-22 20:46:16 +01:00
Lioncash
d456fb85c8
A64: Implement SADDL/SADDL2
2020-04-22 20:46:16 +01:00
Lioncash
5c9e7f328d
A64: Implement USUBL/USUBL2
2020-04-22 20:46:16 +01:00
Lioncash
88d70e3b8a
A64: Implement UADDL/UADDL2
2020-04-22 20:46:16 +01:00
Lioncash
56803f5203
A64: Implement URSRA (vector)
2020-04-22 20:46:16 +01:00
Lioncash
8afdf4b23d
A64: Implement URSHR (vector)
2020-04-22 20:46:16 +01:00
Lioncash
16613ee066
A64: Implement RSHRN/RSHRN2
2020-04-22 20:46:15 +01:00
Lioncash
937990fd2a
A64: Implement SHRN/SHRN2
2020-04-22 20:46:15 +01:00
MerryMage
7969871aa3
A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated
2020-04-22 20:46:15 +01:00
MerryMage
5c95e28ed0
A64: Implement ZIP2
2020-04-22 20:46:15 +01:00
MerryMage
871aefb9a0
decoder/a64: Tweak ordering algorithm
...
Ensuring only instruction families are sorted with each other in
the fashion previously devised does not admit a total ordering.
2020-04-22 20:46:15 +01:00
Lioncash
83ff7a43d1
A64: Implement RBIT (vector)
2020-04-22 20:46:15 +01:00
Lioncash
cf81f04ed3
A64: Implement RAX1
2020-04-22 20:46:15 +01:00
Lioncash
7bcb1c115a
A64: Implement ABS (vector)
2020-04-22 20:46:15 +01:00
Lioncash
84d49309b9
A64: Implement USUBW/USUBW2
2020-04-22 20:46:15 +01:00
Lioncash
e20fce6b5a
A64: Implement SSUBW/SSUBW2
2020-04-22 20:46:15 +01:00
Lioncash
00af6eeab9
A64: Implement SADDW/SADDW2
2020-04-22 20:46:15 +01:00
MerryMage
8bba37089e
A64: Implement UADDW
2020-04-22 20:46:15 +01:00
MerryMage
5c47f03888
A64: Implement FMUL (vector)
2020-04-22 20:46:15 +01:00
Lioncash
a6e264c2dd
A64: Implement UABA
...
Now that we have unsigned absolute difference capabilities, we can just use this to
append onto the result via a vector add.
2020-04-22 20:46:15 +01:00
Lioncash
c2e7364d3e
A64: Implement UABD
2020-04-22 20:46:15 +01:00
Lioncash
94f0fba16b
A64: Implement SHA1H
...
This is a fairly trivial instruction it's essentially:
result = ROL(data, 30);
2020-04-22 20:46:15 +01:00
Lioncash
40ec25356b
A64: NOP immediate variant of PRFM
...
Makes behavior identical to the literal variant of PRFM. Given this is simply a hint instruction,
this is valid behavior. The upside is that we don't fall back to Unicorn unnecessarily whenever
the instruction is encountered.
2020-04-22 20:46:15 +01:00
Lioncash
586b00d11d
A64: Implement REV64
2020-04-22 20:46:15 +01:00
Lioncash
9128988dc3
A64: Implement REV32 (vector)
2020-04-22 20:46:15 +01:00
Lioncash
6ad1bce5e0
A64: Implement REV16 (vector)
2020-04-22 20:46:15 +01:00
Lioncash
7a66224d9a
A64: Implement EOR3 and BCAX
2020-04-22 20:46:15 +01:00
MerryMage
49cc6d7fad
A64: Implement FDIV (vector)
2020-04-22 20:46:15 +01:00
MerryMage
147284427b
A64: Implement USHL
2020-04-22 20:46:15 +01:00
MerryMage
fd8f4c1195
A64: Implement UCVTF (vector, integer), scalar variant
2020-04-22 20:46:15 +01:00
MerryMage
be57608353
A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
2020-04-22 20:46:15 +01:00
MerryMage
e3da92024e
A64: Implement system registers FPCR and FPSR
2020-04-22 20:46:15 +01:00
MerryMage
58fbb3ff1b
A64: Implement NEG (vector)
2020-04-22 20:46:15 +01:00
MerryMage
0575e7421b
A64: Implement FMINNM (scalar)
2020-04-22 20:46:15 +01:00
MerryMage
1c9804ea07
A64: Implement FMAXNM (scalar)
2020-04-22 20:46:15 +01:00
MerryMage
bd2b415850
A64: Implement ADDP (scalar)
2020-04-22 20:46:14 +01:00
MerryMage
9df3793af0
A64: Implement DUP (element), scalar variant
2020-04-22 20:46:14 +01:00
MerryMage
2080a51f41
A64: Implement FMAX (scalar), FMIN (scalar)
2020-04-22 20:46:14 +01:00
MerryMage
0e157b0198
A64: Implement FSQRT (scalar)
2020-04-22 20:46:14 +01:00
MerryMage
8cebb87d0d
A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero)
2020-04-22 20:46:14 +01:00
MerryMage
7f68d556ab
decoder/a64: Rearrange SIMD two-register misc decoders
2020-04-22 20:46:14 +01:00
MerryMage
d5af052f06
A64: Implement CMGE (register)
2020-04-22 20:46:14 +01:00
MerryMage
9d85991906
A64: Implement CMHI, CMHS
2020-04-22 20:46:14 +01:00
MerryMage
0df6725f73
A64: Implement SMAX, SMIN, UMAX, UMIN
2020-04-22 20:46:14 +01:00
MerryMage
adb7f5f86f
A64: Implement CMGT (register)
2020-04-22 20:46:14 +01:00
