MerryMage
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2a6619d59c
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A64: Implement CLREX
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
9f2f08db8d
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a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a6cc667509
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Direct Page Table Access: Handle address spaces less than the full 64-bit in size
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b7a2c1a7df
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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6c4773e85b
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abi: Add RAX to ABI_ALL_CALLER_SAVE
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
f45a5e17c6
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Implement direct page table access
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
8756487554
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A64: Partially implement MRS
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
ef02658049
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fuzz_with_unicorn: Fix read-past-end access via jit_iter
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
bfd65bedfe
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A64: Implement DSB, DMB
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
bfd3e30c75
|
callbacks: Member functions should be const
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
5edd623b9d
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Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
|
Lioncash
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a9153218bd
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A64: Implement NOT (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
2cb0a699ba
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IR: Implement FPMax, FPMin
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
aed4fd3ec3
|
A64: Implement FADD (vector), vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
98c8e7d1af
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IR: Implement FPVectorAdd
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5f77ab28ee
|
A64: Implement SSHLL, SSHLL2
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
eae518a338
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IR: Implement VectorSignExtend
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a90e4955ab
|
CMakeLists: Ignore warnings within xbyak
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
3738043e58
|
A64: Implement DUP (element), vector variant
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
ce7628b6b5
|
load_store_multiple_structures: Improve IR codegen for selem == 1 case
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f1cb5581c9
|
A64: Implement FSUB (vector)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b9cd345ddc
|
IR: Implement FPVectorSub
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
851fc83445
|
emit_x64_vector: EmitOneArgumentFallback
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f378d2ef1b
|
Forward declare IR::Opcode and IR::Type where possible
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
6c9b4f0114
|
A64: Implement CNT
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
303088a51e
|
IR: Implement VectorPopulationCount
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
1dd2b33b87
|
A64: Implement MLS (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5eac3abf52
|
A64: Implement MLA (vector)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bf2cd92da9
|
emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b062266b8e
|
emit_x64_vector: More explicit lambda decay
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
3afd2fcbad
|
A64: Implement MUL (vector)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b6de612e01
|
IR: Implement VectorMultiply
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
90a053a5e4
|
emit_x64_vector: Order alphabetically
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e7041d7196
|
A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a455ff70c9
|
decoder/a64: Don't rearrange unrelated decoders
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
faeb77e8c4
|
A64: Implement SUB (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bd106c3ae7
|
A64: Implement SIMD instruction SSRA, vector variant
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f58aba9871
|
A64: Implement SIMD instruction SSHR, vector variant
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
715ae1c229
|
IR: Implement VectorArithmeticShiftRight
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
653c82d8f0
|
impl: Improve Vpart setter
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e858ce0b35
|
A64: Implement SIMD instructions XTN, XTN2
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
132c783320
|
IR: Implement VectorNarrow
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1423584f9f
|
constant_pool: Allow for 128-bit constants
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
69de50a878
|
emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
cbc9f361b0
|
IR: Implement VectorSub
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
3f93c77ace
|
A64: Implement SIMD instruction USRA, vector variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
fb9d20f27f
|
A64: Implement SIMD instruction USHR, vector variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
b22c5961f9
|
IR: Implement VectorLogicalShiftRight
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7ff280827b
|
A64: Implement SIMD instructions USHLL, USHLL2
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
59ace60b03
|
IR: Implement VectorZeroExtend
|
2020-04-22 20:46:13 +01:00 |
|