MerryMage
52b8039367
A32: Implement VFPv5 VRINT{R,Z}
2020-06-22 19:35:32 +01:00
MerryMage
47bc99ad9f
asimd_load_store_structures: Fix 2-byte aligned vld1.16
...
Previously incorrectly undefined
2020-06-22 18:46:22 +01:00
Lioncash
dd8d5497da
A32: Implement ASIMD VQRDMULH
2020-06-22 17:31:57 +01:00
Lioncash
0b7a111b54
A32: Implement ASIMD VQDMULH
2020-06-22 17:31:57 +01:00
Lioncash
39488e4aad
A32: Implement ASIMD VRSHRN
2020-06-21 23:15:43 +01:00
Lioncash
86b0e5c1c5
A32: Implement ASIMD VQSHRN
2020-06-21 23:15:43 +01:00
Lioncash
85222e3e65
A32: Implement ASIMD VQSHRUN
...
We can leverage ShiftRightNarrowing() to implement this.
2020-06-21 23:15:43 +01:00
MerryMage
562a98bcf9
A32: Implement ASIMD VCVT (between floating-point and fixed-point)
2020-06-21 20:23:40 +01:00
MerryMage
6f56043a73
A32: Implement ASIMD VFMA, VFMS
2020-06-21 20:21:53 +01:00
Lioncash
aa0358d324
A32: Implement ASIMD VMLAL/VMLSL (integer)
2020-06-21 20:03:19 +01:00
Lioncash
eab26b404a
A32: Implement ASIMD VABAL
2020-06-21 20:01:08 +01:00
Lioncash
98581839ca
A32: Implement ASIMD VABDL
2020-06-21 19:55:00 +01:00
MerryMage
db85e7ced5
asimd: Add missing three registers of different lengths instructions
2020-06-21 19:54:32 +01:00
Lioncash
95919594d1
A32: Implement ASIMD VQSHL/VQSHLU (immediate)
2020-06-21 19:26:30 +01:00
MerryMage
3557576ece
A32: Implement ASIMD AESD, AESE, AESIMC, AESMC
2020-06-21 18:39:57 +01:00
Fernando Sahmkow
2fa1c1d13c
A32: Allow cleaning up exclusive state from the interface.
...
This function is normally required for emulating certain OS mechanisms.
2020-06-21 18:18:33 +01:00
MerryMage
df58a429ee
A32: Implement ASIMD VQRSHRN
2020-06-21 17:41:18 +01:00
MerryMage
589d717af5
A32: Implement ASIMD VQRSHRUN
2020-06-21 17:41:18 +01:00
MerryMage
e009d99924
A32: Implement ASIMD VSHRN
2020-06-21 17:41:18 +01:00
MerryMage
473949d486
asimd_load_store_structures: Suppress MSVC shift warning
2020-06-21 17:41:18 +01:00
MerryMage
8f0f1cfd66
A32: Implement ASIMD VST{1,2,3,4} (single n-element structure from one lane)
2020-06-21 16:27:33 +01:00
MerryMage
5a597f415c
A32: Implement A32 VLD{1,2,3,4} (single n-element structure to one lane)
2020-06-21 16:22:43 +01:00
MerryMage
f221912409
bit_util: Bits without template arguments
2020-06-21 16:07:59 +01:00
MerryMage
3202e4c539
A32: Implement ASIMD VLD{1,2,3,4} (single n-element structure to all lanes)
2020-06-21 15:25:26 +01:00
MerryMage
d7197745ac
emit_x64_vector_floating_point: fpcr_controlled is unused when fsize == 16 in EmitFPVectorToFixed
2020-06-21 14:46:06 +01:00
MerryMage
b32fc5ab0f
a64_emit_x64: EmitVAddrLookup: Use bzhi instruction when silently_mirror_page_table is active and BMI2 is available
2020-06-21 14:46:06 +01:00
MerryMage
809dfe9c54
A32: Implement ASIMD VCVT (between floating-point and integer)
2020-06-21 14:28:25 +01:00
MerryMage
43a4b2a0b8
ir_emitter: Remove dummy fpcr_controlled arguments from scalar FP instructions
2020-06-21 14:28:25 +01:00
MerryMage
c836b389c8
emit_x64_vector_floating_point: Add fpcr_controlled argument to all IR instructions
2020-06-21 14:28:25 +01:00
MerryMage
33a81dae68
asimd: VEXT was being shadowed
2020-06-21 13:12:19 +01:00
MerryMage
bf093395d8
A32: Implement ASIMD VMOVN
2020-06-21 12:35:39 +01:00
MerryMage
c7785cd982
A32: Implement ASIMD VUZP and VZIP
2020-06-21 12:34:55 +01:00
MerryMage
603cd09c8f
A32: Implement ASIMD VTRN
2020-06-21 12:14:13 +01:00
MerryMage
a8b481ab63
simd_permute: Implement TRN{1,2} in terms of VectorTranspose
2020-06-21 12:14:13 +01:00
MerryMage
7d1e103ff5
IR: Implement VectorTranspose
2020-06-21 12:14:13 +01:00
MerryMage
9cc11681dc
A32: Implement ASIMD VMLAL, VMLSL, VMULL (scalar)
2020-06-21 10:31:30 +01:00
MerryMage
69a1d58a2b
A32: Implement ASIMD VMULL
2020-06-21 10:00:24 +01:00
Lioncash
8c23f02330
A32: Implement ASIMD VABD
2020-06-21 07:54:21 +01:00
Lioncash
fc1633a2ea
A32: Implement ASIMD VABA
2020-06-21 07:54:21 +01:00
Lioncash
bdb92f7055
asimd: Split out VABA/VABD decoders
...
These differ in bit encodings anyway
2020-06-21 07:54:21 +01:00
Lioncash
230fa02648
A32: Implement ASIMD VMLA/VMLS (scalar)
...
While we're at it, we can join the implementation of VMUL into a common
function.
2020-06-21 07:51:17 +01:00
MerryMage
239ee289cf
A32: Implement VDUP (scalar)
2020-06-21 00:22:42 +01:00
Lioncash
a8efe3f0f5
A32: Implement ASIMD VACGE/VACGT
2020-06-21 00:02:48 +01:00
Lioncash
e319257ec0
A32: Implement VCEQ/VCGE/VCGT (floating point)
2020-06-21 00:02:48 +01:00
Lioncash
faefb264a6
A32: Implement ASIMD VCEQ (integer)
2020-06-21 00:02:48 +01:00
Lioncash
7276993352
A32: Implement ASIMD VCGE (integer)
2020-06-21 00:02:48 +01:00
Lioncash
7292320445
A32: Implement ASIMD VCGT (integer)
2020-06-21 00:02:48 +01:00
MerryMage
fda4e11887
A32: Implement ASIMD VMOV (general-purpose register to scalar)
2020-06-20 23:40:48 +01:00
MerryMage
7ec22b4e1d
A32: Implement ASIMD VMOV (scalar to general-purpose register)
2020-06-20 23:30:56 +01:00
MerryMage
8bbc9fdbb6
A32: Implement ASIMD VTBX
2020-06-20 22:35:31 +01:00
Lioncash
06f7229c57
A32: Implement ASIMD VPADAL (integer)
2020-06-20 22:28:47 +01:00
Lioncash
266c6a2000
A32: Implement ASIMD VPADDL (integer)
2020-06-20 22:28:47 +01:00
Lioncash
4bb286ac23
A32: Implement ASIMD VPADD (integer)
2020-06-20 21:22:14 +01:00
Lioncash
1ffeeeb6a2
A32: Implement ASIMD VMAX/VMIN (integer)
2020-06-20 21:20:47 +01:00
Lioncash
945b757b6c
A32: Implement ASIMD VMLA/VMLS (integer)
2020-06-20 21:20:21 +01:00
MerryMage
715db8381f
A32: Implement ASIMD VMUL (scalar)
2020-06-20 20:34:08 +01:00
MerryMage
b0beecdd41
A32: Implement ASIMD VTBL
2020-06-20 19:25:14 +01:00
MerryMage
28f27bc19d
A32: Implement ASIMD VEXT
2020-06-20 19:05:14 +01:00
MerryMage
e8c460c167
A32: Implement ASIMD VDUP (ARM core register)
2020-06-20 16:02:43 +01:00
MerryMage
15ee562dd0
decoder/asimd: Add misc data-processing instructions
2020-06-20 15:39:00 +01:00
MerryMage
92cb4a5a34
A32: Implement ASIMD VRSQRTE
2020-06-20 15:13:22 +01:00
MerryMage
6f59c2cd8e
A32: Implement ASIMD VRECPE
2020-06-20 15:07:06 +01:00
MerryMage
d3dc50d718
A32: Implement ASIMD VRSQRTS
2020-06-20 15:06:06 +01:00
MerryMage
8f506c80c3
A32: Implement ASIMD VRECPS
2020-06-20 14:39:05 +01:00
MerryMage
9eef4f7471
A32: Implement ASIMD VMLA, VMLS (floating-point)
2020-06-20 14:31:06 +01:00
MerryMage
60f6e729ac
A32: Implement ASIMD VABD (floating-point)
2020-06-20 14:25:04 +01:00
MerryMage
f58e247ef3
A32: Implement ASIMD VPADD (floating-point)
2020-06-20 14:25:04 +01:00
MerryMage
e006f0a205
A32: Implement ASIMD VSUB (floating-point)
2020-06-20 14:20:28 +01:00
MerryMage
4c939b9d0a
A32: Implement ASIMD VADD (floating-point)
2020-06-20 14:20:28 +01:00
MerryMage
5ec8e48593
A32: Implement ASIMD VMUL (floating-point)
...
* Also add fpcr_controlled arguments to FPVectorMul IR instruction
* Merge ASIMD floating-point instruction implementations
2020-06-20 14:20:28 +01:00
MerryMage
bb4f3aa407
A32: Implement ASIMD VMAX, VMIN (floating-point)
2020-06-20 03:21:07 +01:00
Lioncash
8d067d5d60
A32: Implement ASIMD VMUL (integer and polynomial)
2020-06-20 00:53:56 +01:00
Lioncash
ed6ca58058
A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero
...
Fairly self-explanatory, we can leverage the existing IR functions for
the purpose of these instructions.
In the integer case, we can just insert function pointers
into an array and index it, given all comparison primitives exist
already for the integer side of things.
2020-06-20 00:50:40 +01:00
MerryMage
656419286c
ir: Add fpcr_controlled argument to FPVector{Equal,Greater,GreaterEqual}
2020-06-20 00:50:40 +01:00
MerryMage
1b3a70a83c
backend/x64: Implement separate MSXCSR for ASIMDStandardValue
2020-06-20 00:00:36 +01:00
MerryMage
d3664b03fe
ir_emitter: Default fpcr_controlled arguments to true
2020-06-19 22:51:23 +01:00
Lioncash
794440cf8d
A32: Implement ASIMD VRSHL
2020-06-19 21:27:48 +01:00
Lioncash
682621ef1a
A32: Implement ASIMD VQSHL (register)
2020-06-19 21:27:48 +01:00
Lioncash
e46fb98cc5
A32: Implement ASIMD VSHL (register)
2020-06-19 21:27:48 +01:00
MerryMage
ad96b2b18d
VFPv5: Implement VCVT{A,N,P,M}
2020-06-19 20:31:43 +01:00
MerryMage
6a965b80d6
VFPv5: Implement VRINT{A,N,P,M}
2020-06-19 20:24:13 +01:00
MerryMage
3e252cdbfc
VFPv5: Implement VSEL
2020-06-19 19:44:45 +01:00
MerryMage
669d05caca
VFPv5: Implement VMINNM
2020-06-19 19:44:45 +01:00
MerryMage
6e7ea151a3
VFPv5: Implement VMAXNM
2020-06-19 19:39:01 +01:00
MerryMage
4df3b2f97f
vfp: Add decoders for VFPv5
...
These instructions were introduced in the Cortex-M7
2020-06-19 19:24:32 +01:00
MerryMage
55c021fe82
emit_x64_aes: AESNI implementations of all opcodes
2020-06-19 12:11:45 +01:00
Lioncash
551e207661
A32: Implement ASIMD VSUB (integer)
2020-06-19 11:31:38 +01:00
Lioncash
4d6f68525d
A32: Implement ASIMD VADD (integer)
2020-06-19 11:31:38 +01:00
Lioncash
fbdae61c13
A32: Implement ASIMD VMVN (register)
...
Fairly straightforward
2020-06-19 11:31:14 +01:00
MerryMage
b759773b3b
a32_emit_x64: EmitVAddrLookup: Use 64-bit registers where required
2020-06-19 00:44:52 +01:00
merry
687c604197
Merge pull request #532 from lioncash/shift
...
A32: Implement several ASIMD shift instructions
2020-06-19 00:22:18 +01:00
MerryMage
7dd9901de2
a32_emit_x64: Incorrect type in ExclusiveWriteMemory
2020-06-19 00:19:46 +01:00
Lioncash
00b2f9b319
asimd: Prevent misdecodes from occurring
...
Pointed out by Mary when reviewing the shift code.
2020-06-18 15:04:48 -04:00
MerryMage
87f6e412d0
emit_x64_vector: SSE4.1 implementation of EmitVectorPolynomialMultiply{Long}8
2020-06-18 18:44:00 +01:00
MerryMage
f5b41aabc6
emit_x64_vector: Implement EmitVectorPolynomialMultiplyLong64 in terms of pclmulqdq
2020-06-18 18:04:23 +01:00
MerryMage
d34763242c
Revert "A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero"
...
This reverts commit 179951b10f
2020-06-18 17:38:40 +01:00
Lioncash
179951b10f
A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero
...
Fairly self-explanatory, we can leverage the existing IR functions for
the purpose of these instructions.
In the integer case, we can just insert function pointers
into an array and index it, given all comparison primitives exist
already for the integer side of things.
2020-06-18 17:01:57 +01:00
Lioncash
6ca20c2fe3
A32: Implement ASIMD VSLI
2020-06-18 11:51:08 -04:00
Lioncash
887732d8a8
A32: Implement ASIMD VSRI
2020-06-18 11:28:12 -04:00
Lioncash
8b98c91ecc
A32: Implement ASIMD VSHL
2020-06-18 11:18:33 -04:00
Lioncash
69c999bc66
A32: Implement ASIMD VRSRA
...
Now that we have the accumulation and rounding code in place, VRSRA is
extremely trivial to implement.
2020-06-18 11:03:39 -04:00
Lioncash
14fdd15199
A32: Implement ASIMD VRSHR
2020-06-18 11:00:45 -04:00
Lioncash
276e0b71dc
A32: Implement ASIMD VSRA
2020-06-18 11:00:27 -04:00
Lioncash
054dff7cd5
A32: Implement ASIMD VTST
2020-06-18 15:34:05 +01:00
Lioncash
6c142bc5cc
A32: Implement ASIMD VSHR
2020-06-18 10:30:20 -04:00
MerryMage
13367a7efd
A64: Match A32 page_table code
...
Here we increase the similarity between the A64 and A32 front-ends in terms of their
page_table handling code. In this commit, we:
* Reserve and use r14 as a register to store the page_table pointer.
* Align the code to be more similar in structure.
* Add a conf member to A32EmitContext.
* Remove scratch argument from EmitVAddrLookup.
2020-06-18 12:22:59 +01:00
Lioncash
08350d06f1
A32: Implement ASIMD VQNEG
2020-06-18 09:49:29 +01:00
Lioncash
f6b665f5a4
A32: Implement ASIMD VQABS
2020-06-18 09:49:29 +01:00
MerryMage
b88c291f81
A32: Detect misaligned memory accesses
...
This avoids issues with misaligned memory accesses writing into the next page.
2020-06-17 17:51:37 +01:00
MerryMage
9f3277540a
Merge A32 and A64 exclusive monitors
2020-06-17 10:33:09 +01:00
Lioncash
4b371c0445
A32: Implement ASIMD VREV{16, 32, 64}
2020-06-17 10:21:59 +01:00
Lioncash
6dd2c94095
A32: Implement ASIMD VABS
...
Very similar to VNEG in that the only thing that differs is the function
called.
2020-06-16 22:42:18 +01:00
MerryMage
53422bec46
a64_emit_x64: Reduce code duplication in exclusive memory code
2020-06-16 18:16:33 +01:00
MerryMage
a1c9bb94a8
A32: Add yuzu-specific hacks
2020-06-16 17:54:21 +01:00
MerryMage
2c1a4843ad
A32 global exlcusive monitor
2020-06-16 17:54:21 +01:00
MerryMage
58abdcce5b
backend/x64/a32_*: Rename config to conf
...
Standardize on one name for both a32_* and a64_*.
2020-06-16 14:56:44 +01:00
MerryMage
7ea521b8bf
a32_emit_x64: Change ExclusiveWriteMemory64 to require a single U64 argument
2020-06-16 13:32:50 +01:00
MerryMage
aa341b7eea
a32_emit_x64: Make ExclusiveWrite a member function of A32EmitX64
2020-06-16 13:03:17 +01:00
MerryMage
34ef5142e3
a32_emit_x64: Specify callback as template argument
...
Removes unnecessary switch statement.
2020-06-16 10:23:51 +01:00
MerryMage
58b2c83944
a32_emit_x64: Reduce mov code duplication in {Read,Write}Memory
2020-06-16 10:14:06 +01:00
Lioncash
aabd0d824d
A32: Add immediate creation helper
...
Provides the same helper function that exists within the A64 frontend
for creating immediate values.
2020-06-16 09:54:28 +01:00
Lioncash
93ed3441b7
A32: Implement ASIMD VCLS/VCLZ/VCNT
2020-06-16 09:54:28 +01:00
Lioncash
15b3de95e4
A32: Implement VNEG
2020-06-16 01:53:21 +01:00
MerryMage
2796a85096
interface/a32: Remove descriptor argument from Disassemble
2020-06-12 15:27:42 +01:00
MerryMage
3ccc415c52
emit_x64_saturation: Improve codegen for saturated result in EmitSignedSaturation
2020-06-12 15:24:37 +01:00
MerryMage
e953f67201
emit_x64_packed: PackedAbsDiffSumS8: Fix case when bits above the lower 32 bits are not zero
2020-06-12 15:24:09 +01:00
MerryMage
c4cf0b3e47
exception_handler_posix: Just disable fastmem if initialization fails
2020-06-10 22:52:27 +01:00
MerryMage
55bddc767f
backend/x64: Touch PEXT/PDEP code
...
* Use pext/pdep where not previously used
* Limit pext/pdep to non-AMD platforms due to slowness on AMD
* Use imul/and as alternatives for AMD and non-BMI2 platforms
2020-06-10 22:30:22 +01:00
MerryMage
f495018f53
block_of_code: Encapsulate CPU feature detection code
2020-06-09 21:25:57 +01:00
MerryMage
feddf69cb4
emit_x64_crc32: Use same constants
2020-06-06 20:46:09 +01:00
MerryMage
66a356e6cb
emit_x64_crc32: Further improvements to codegen
2020-06-06 19:04:20 +01:00
MerryMage
bb203429c6
crc32: Remove unnecessary masking
2020-06-04 20:33:46 +01:00
MerryMage
bcde135c23
emit_x64_crc32: Improve 64-bit PCLMULQDQ implementation of EmitCRC32ISO
...
Reduce number of PCLMULQDQs to 3
2020-06-04 19:23:51 +01:00
MerryMage
0f9c70ff42
emit_x64_crc32: Improve PCLMULQDQ implementation of EmitCRC32ISO
...
Remove use of pshufd
2020-06-03 18:55:58 +01:00
MerryMage
fa6aee434e
emit_x64_crc32: PCLMULQDQ implementation of EmitCRC32ISO
2020-06-03 11:16:53 +01:00
MerryMage
b47adaee1d
emit_x64_vector: SSSE3 implementation of EmitVectorExtract
2020-06-01 15:41:36 +01:00
MerryMage
f3845cea9a
A32: Implement ASIMD VQSUB instruction
2020-05-30 18:19:17 +01:00
MerryMage
16ff880f8f
A32: Implement ASIMD VQADD
2020-05-30 16:09:37 +01:00
MerryMage
174fbb74c5
simd_three_same: Use VectorSaturated{Signed,Unsigned}{Add,Sub} in SaturatingArithmeticOperation
2020-05-30 15:55:32 +01:00
MerryMage
4e90754873
IR: Implement VectorSaturated{Signed,Unsigned}{Add,Sub}
2020-05-30 15:55:32 +01:00
MerryMage
3a50d444dc
A32: Implement ASIMD VHSUB
2020-05-28 22:29:00 +01:00
MerryMage
205e6c5a56
A32: Implement ASIMD VRHADD
2020-05-28 22:29:00 +01:00
MerryMage
946eb03a3b
A32: Implement ASIMD VHADD
2020-05-28 22:29:00 +01:00
MerryMage
f8062345bb
asimd_two_regs_misc: Use {Get,Set}Vector
2020-05-28 21:05:30 +01:00
MerryMage
11cec1e3b6
asimd_three_same: Use {Get,Set}Vector
2020-05-28 21:05:16 +01:00
MerryMage
7d0b16de32
asimd_one_reg_modified_immediate: Use {Get,Set}Vector
2020-05-28 20:40:26 +01:00
MerryMage
cae857b8c8
verification_pass: Have an appropriate assertion message
2020-05-28 20:40:11 +01:00
MerryMage
ebddf6cca0
basic_block: Allow printing of invalid instruction pointers
2020-05-28 20:39:50 +01:00
MerryMage
07108246cf
A32/IR: Add SetVector and GetVector
2020-05-28 20:39:19 +01:00
MerryMage
93c289b54f
Use tsl::robin_map and tsl::robin_set
...
Replace std::unordered_map and std::unordered_set with the above.
Better performance profile.
2020-05-26 20:51:48 +01:00
