Lioncash
53f1a52be9
thumb32: Implement SMMLS{R}
2021-02-07 13:23:21 -05:00
Lioncash
0c542777b0
thumb32: Implement SMMLA{R}
2021-02-07 13:14:47 -05:00
Lioncash
b6add0ddf4
thumb32: Implement SMMUL{R}
2021-02-07 13:11:25 -05:00
Lioncash
44f4f437a7
thumb32: Implement SMUSD
2021-02-07 13:07:38 -05:00
Lioncash
4d9a7308ac
thumb32: Implement SMUAD
2021-02-07 13:04:18 -05:00
Lioncash
1e06231575
thumb32: Implement SMLAXY
2021-02-07 12:39:12 -05:00
Lioncash
1cd10e3214
thumb32: Implement SMULXY
2021-02-07 12:27:40 -05:00
MerryMage
1e29ef8b0e
A32/location_descriptor: Implement SetIT
2021-02-07 14:18:03 +00:00
MerryMage
5e75bd41a4
ITState: Handle not-in-IT-block case in Cond
2021-02-07 14:17:46 +00:00
MerryMage
946dbb5818
ITSTate: Correct ITState::Advance
2021-02-07 13:21:45 +00:00
MerryMage
1c5f6882f0
A32/translate_thumb: Correct IsThumb16
2021-02-07 12:18:45 +00:00
MerryMage
7e5ae6076a
A32: Add arch_version option
2021-02-07 12:13:14 +00:00
Lioncash
50d81f95e5
thumb32: Implement USADA8
2021-02-07 09:57:34 +00:00
Lioncash
ed453aa52d
thumb32: Implement USAD8
2021-02-07 09:57:34 +00:00
Lioncash
b07fab604f
thumb32: Implement MLS
2021-02-07 09:57:34 +00:00
Lioncash
cf5058bccb
thumb32: Implement MLA
2021-02-07 09:57:34 +00:00
Lioncash
153d87c843
thumb32: Implement MUL
2021-02-07 09:57:34 +00:00
MerryMage
8b612edb75
translate_thumb: Fix bug in TranslateSingleThumbInstruction
2021-02-06 21:26:44 +00:00
MerryMage
39644d69ee
A32/decode: Split thumb32
2021-02-06 21:26:42 +00:00
MerryMage
6d0a049fb2
A32/decode: Split thumb16
2021-02-06 21:25:24 +00:00
MerryMage
ac9e1ccb1c
A32/thumb16: Fix bug in CBZ/CBNZ
2021-02-06 21:25:24 +00:00
Lioncash
23619c8c6a
thumb32: Implement SHSUB8/UHSUB8
2021-02-01 17:50:46 -05:00
Lioncash
9d2570470e
thumb32: Implement SHADD8/UHADD8
2021-02-01 17:50:46 -05:00
Lioncash
afad76078d
thumb32: Implement SHSUB16/UHSUB16
2021-02-01 17:50:46 -05:00
Lioncash
51b7c32d02
thumb32: Implement SHSAX/UHSAX
2021-02-01 17:50:46 -05:00
Lioncash
f0a219fcd0
thumb32: Implement SHASX/UHASX
2021-02-01 17:50:46 -05:00
Lioncash
94f8efbb03
thumb32: Implement SHADD16/UHADD16
2021-02-01 17:50:46 -05:00
Lioncash
aa49b0db89
thumb32: Implement QSUB8/UQSUB8
2021-02-01 17:50:46 -05:00
Lioncash
874ab6a7b6
thumb32: Implement QADD8/UQADD8
2021-02-01 17:50:46 -05:00
Lioncash
d923fb24c6
thumb32: Implement QSUB16/UQSUB16
2021-02-01 17:50:46 -05:00
Lioncash
416fe26df0
thumb32: Implement QSAX/UQSAX
2021-02-01 17:50:14 -05:00
Lioncash
ad7c8bd042
thumb32: Implement QASX/UQASX
2021-02-01 17:31:30 -05:00
Lioncash
f52b8f924c
thumb32: Implement QADD16/UQADD16
2021-02-01 17:31:30 -05:00
Lioncash
6f593da41b
thumb32: Implement SSUB8/USUB8
2021-02-01 17:31:27 -05:00
Lioncash
271354ee95
thumb32: Implement SADD8/UADD8
2021-02-01 16:44:11 -05:00
Lioncash
8f42fd5c0e
thumb32: Implement SSUB16/USUB16
2021-02-01 16:41:02 -05:00
Lioncash
0e28c63456
thumb32: Implement SSAX/USAX
2021-02-01 16:36:18 -05:00
Lioncash
21e404d3ab
thumb32: Implement SASX/UASX
2021-02-01 16:31:25 -05:00
Lioncash
d529417875
thumb32: Implement SADD16/UADD16
2021-02-01 16:19:33 -05:00
merry
0e26e8a531
Merge pull request #569 from lioncash/t32-misc
...
thumb32: Implement miscellaneous category instructions
2021-02-01 21:06:36 +00:00
Lioncash
36fc596a51
thumb32: Implement QADD
2021-02-01 15:44:09 -05:00
Lioncash
cd6e4c7afd
thumb32: Implement QSUB
2021-02-01 15:42:14 -05:00
Lioncash
65365ad2a3
thumb32: Implement QDADD
2021-02-01 15:39:39 -05:00
Lioncash
d96c8c662b
thumb32: Implement QDSUB
2021-02-01 15:35:09 -05:00
Lioncash
c60cf921ee
thumb32: Implement REV
2021-02-01 15:30:40 -05:00
Lioncash
0304dc7ce4
thumb32: Implement REV16
2021-02-01 15:27:31 -05:00
Lioncash
cee31c5274
thumb32: Implement RBIT
2021-02-01 15:20:24 -05:00
Lioncash
e2bc7eeb93
thumb32: Implement REVSH
2021-02-01 15:16:53 -05:00
MerryMage
e01583abba
A64/system: Reorder fields of SystemRegisterEncoding
...
Matches manual, which allows for easier verification of correctness.
2021-02-01 20:01:39 +00:00
Lioncash
1ad99bb9b5
thumb32: Implement SEL
2021-02-01 15:01:21 -05:00
Lioncash
8d53048750
thumb32: Implement CLZ
...
Also fleshes out the generator to allow for generating thumb32
instructions as well.
2021-02-01 14:54:04 -05:00
MerryMage
f2345c1590
A64/system: Implement MSR/MRS for NZCV
2021-02-01 19:52:49 +00:00
MerryMage
8c4463a0c1
emit_x64_data_processing: EmitSub: Use cmp where possible
2021-01-01 19:37:47 +00:00
MerryMage
42059edca4
decoder_detail: Fix bit_position and one unused warnings in GetArgInfo
2020-12-28 23:34:23 +00:00
ReinUsesLisp
ba6654b0e7
location_descriptor: Fix compare operator for single stepping
...
Compare `single_stepping` with the other's value instead of comparing it
with the local value.
2020-12-01 09:11:40 +00:00
MerryMage
46f96904db
decoder_detail: Add check for N==0 to GetArgInfo
2020-10-11 22:12:21 +01:00
Lioncash
0e1112b7df
Revert "basic_block: Mark move constructor and assignment as noexcept"
...
This reverts commit 4f12e86ebb
2020-08-14 16:49:40 -04:00
Lioncash
4f12e86ebb
basic_block: Mark move constructor and assignment as noexcept
...
Allows the type to play nicely with standard library facilities better
(also we shouldn't be throwing in move operations to begin with).
2020-08-14 14:38:28 -04:00
MerryMage
82868034d3
A32/ASIMD: Ensure decoder table is correct
...
* Raise a DecoderError instead of ASSERT-ing on a decode error
* Correct ASIMD decode table
* Write a test which verifies every possible ASIMD instruction
2020-07-05 18:45:42 +01:00
MerryMage
3c742960a9
simd_three_same: Ensure zero in upper for PairedMinMaxOperation
2020-07-04 11:25:36 +01:00
MerryMage
735738c7b6
A32: Implement ASIMD VPMAX, VPMIN (floating-point)
2020-07-04 11:04:10 +01:00
MerryMage
88e74cb2ba
A32: Implement ASIMD VPMAX, VPMIN (integer)
2020-07-04 11:04:10 +01:00
MerryMage
d9914b1d51
simd_permute: Implement VectorUnzip with deinterleave lower
2020-07-04 11:04:10 +01:00
MerryMage
f35aaa017c
IR: Add VectorDeinterleave{Even,Odd}Lower
2020-07-04 11:04:10 +01:00
MerryMage
df477c46c2
asimd_load_store_structures: VST1 undef correction
2020-07-04 11:04:10 +01:00
MerryMage
3eed024caf
asimd_three_same: Ignore Q=1 for VPADD (floating-point)
2020-07-04 11:04:10 +01:00
MerryMage
896cb46c89
asimd_*: Standardize order of n and m to reduce confusion
2020-07-04 11:04:10 +01:00
Merry
4f967387c0
asimd_three_regs: Reimplement asimd_VMLAL in terms of WideInstruction
2020-06-27 13:06:46 +01:00
Merry
7997404ee7
A32: Implement ASIMD V{ADD,SUB}{W,L}
2020-06-27 12:58:47 +01:00
Merry
868bd00ab5
A32: Rearrange translators for ASIMD Three Registers
...
* Separate Three Registers with Different Lengths from Same Lengths decoders
2020-06-27 11:15:07 +01:00
MerryMage
8a1f106dba
decoder/asimd: Correct names of scalar exceptions
2020-06-25 17:40:11 +01:00
MerryMage
495f58eed8
A32: Implement ASIMD VSHLL
2020-06-24 23:47:13 +01:00
MerryMage
ed48a9d7d5
A32: Implement VFPv5 VRINTX
2020-06-24 22:31:58 +01:00
Lioncash
b5df8d1ef8
A32: Implement ASIMD VQDMULL (scalar)
2020-06-23 18:19:42 +01:00
Lioncash
20a2bf29fc
A32: Implement ASIMD VQRDMULH (scalar)
2020-06-23 18:19:42 +01:00
Lioncash
ab5efe8632
A32: Implement ASIMD VQDMULH (scalar)
2020-06-23 18:19:42 +01:00
MerryMage
3ea49fc6d6
A32: Implement VFPv3 VCT (between floating-point and fixed-point)
2020-06-22 22:08:58 +01:00
MerryMage
48b2ffdde9
A32: Implement ASIMD VQMOVUN, VQMOVN
2020-06-22 20:02:52 +01:00
MerryMage
52b8039367
A32: Implement VFPv5 VRINT{R,Z}
2020-06-22 19:35:32 +01:00
MerryMage
47bc99ad9f
asimd_load_store_structures: Fix 2-byte aligned vld1.16
...
Previously incorrectly undefined
2020-06-22 18:46:22 +01:00
Lioncash
dd8d5497da
A32: Implement ASIMD VQRDMULH
2020-06-22 17:31:57 +01:00
Lioncash
0b7a111b54
A32: Implement ASIMD VQDMULH
2020-06-22 17:31:57 +01:00
Lioncash
39488e4aad
A32: Implement ASIMD VRSHRN
2020-06-21 23:15:43 +01:00
Lioncash
86b0e5c1c5
A32: Implement ASIMD VQSHRN
2020-06-21 23:15:43 +01:00
Lioncash
85222e3e65
A32: Implement ASIMD VQSHRUN
...
We can leverage ShiftRightNarrowing() to implement this.
2020-06-21 23:15:43 +01:00
MerryMage
562a98bcf9
A32: Implement ASIMD VCVT (between floating-point and fixed-point)
2020-06-21 20:23:40 +01:00
MerryMage
6f56043a73
A32: Implement ASIMD VFMA, VFMS
2020-06-21 20:21:53 +01:00
Lioncash
aa0358d324
A32: Implement ASIMD VMLAL/VMLSL (integer)
2020-06-21 20:03:19 +01:00
Lioncash
eab26b404a
A32: Implement ASIMD VABAL
2020-06-21 20:01:08 +01:00
Lioncash
98581839ca
A32: Implement ASIMD VABDL
2020-06-21 19:55:00 +01:00
MerryMage
db85e7ced5
asimd: Add missing three registers of different lengths instructions
2020-06-21 19:54:32 +01:00
Lioncash
95919594d1
A32: Implement ASIMD VQSHL/VQSHLU (immediate)
2020-06-21 19:26:30 +01:00
MerryMage
3557576ece
A32: Implement ASIMD AESD, AESE, AESIMC, AESMC
2020-06-21 18:39:57 +01:00
MerryMage
df58a429ee
A32: Implement ASIMD VQRSHRN
2020-06-21 17:41:18 +01:00
MerryMage
589d717af5
A32: Implement ASIMD VQRSHRUN
2020-06-21 17:41:18 +01:00
MerryMage
e009d99924
A32: Implement ASIMD VSHRN
2020-06-21 17:41:18 +01:00
MerryMage
473949d486
asimd_load_store_structures: Suppress MSVC shift warning
2020-06-21 17:41:18 +01:00
MerryMage
8f0f1cfd66
A32: Implement ASIMD VST{1,2,3,4} (single n-element structure from one lane)
2020-06-21 16:27:33 +01:00
MerryMage
5a597f415c
A32: Implement A32 VLD{1,2,3,4} (single n-element structure to one lane)
2020-06-21 16:22:43 +01:00
MerryMage
3202e4c539
A32: Implement ASIMD VLD{1,2,3,4} (single n-element structure to all lanes)
2020-06-21 15:25:26 +01:00
MerryMage
809dfe9c54
A32: Implement ASIMD VCVT (between floating-point and integer)
2020-06-21 14:28:25 +01:00
MerryMage
43a4b2a0b8
ir_emitter: Remove dummy fpcr_controlled arguments from scalar FP instructions
2020-06-21 14:28:25 +01:00
MerryMage
c836b389c8
emit_x64_vector_floating_point: Add fpcr_controlled argument to all IR instructions
2020-06-21 14:28:25 +01:00
MerryMage
33a81dae68
asimd: VEXT was being shadowed
2020-06-21 13:12:19 +01:00
MerryMage
bf093395d8
A32: Implement ASIMD VMOVN
2020-06-21 12:35:39 +01:00
MerryMage
c7785cd982
A32: Implement ASIMD VUZP and VZIP
2020-06-21 12:34:55 +01:00
MerryMage
603cd09c8f
A32: Implement ASIMD VTRN
2020-06-21 12:14:13 +01:00
MerryMage
a8b481ab63
simd_permute: Implement TRN{1,2} in terms of VectorTranspose
2020-06-21 12:14:13 +01:00
MerryMage
7d1e103ff5
IR: Implement VectorTranspose
2020-06-21 12:14:13 +01:00
MerryMage
9cc11681dc
A32: Implement ASIMD VMLAL, VMLSL, VMULL (scalar)
2020-06-21 10:31:30 +01:00
MerryMage
69a1d58a2b
A32: Implement ASIMD VMULL
2020-06-21 10:00:24 +01:00
Lioncash
8c23f02330
A32: Implement ASIMD VABD
2020-06-21 07:54:21 +01:00
Lioncash
fc1633a2ea
A32: Implement ASIMD VABA
2020-06-21 07:54:21 +01:00
Lioncash
bdb92f7055
asimd: Split out VABA/VABD decoders
...
These differ in bit encodings anyway
2020-06-21 07:54:21 +01:00
Lioncash
230fa02648
A32: Implement ASIMD VMLA/VMLS (scalar)
...
While we're at it, we can join the implementation of VMUL into a common
function.
2020-06-21 07:51:17 +01:00
MerryMage
239ee289cf
A32: Implement VDUP (scalar)
2020-06-21 00:22:42 +01:00
Lioncash
a8efe3f0f5
A32: Implement ASIMD VACGE/VACGT
2020-06-21 00:02:48 +01:00
Lioncash
e319257ec0
A32: Implement VCEQ/VCGE/VCGT (floating point)
2020-06-21 00:02:48 +01:00
Lioncash
faefb264a6
A32: Implement ASIMD VCEQ (integer)
2020-06-21 00:02:48 +01:00
Lioncash
7276993352
A32: Implement ASIMD VCGE (integer)
2020-06-21 00:02:48 +01:00
Lioncash
7292320445
A32: Implement ASIMD VCGT (integer)
2020-06-21 00:02:48 +01:00
MerryMage
fda4e11887
A32: Implement ASIMD VMOV (general-purpose register to scalar)
2020-06-20 23:40:48 +01:00
MerryMage
7ec22b4e1d
A32: Implement ASIMD VMOV (scalar to general-purpose register)
2020-06-20 23:30:56 +01:00
MerryMage
8bbc9fdbb6
A32: Implement ASIMD VTBX
2020-06-20 22:35:31 +01:00
Lioncash
06f7229c57
A32: Implement ASIMD VPADAL (integer)
2020-06-20 22:28:47 +01:00
Lioncash
266c6a2000
A32: Implement ASIMD VPADDL (integer)
2020-06-20 22:28:47 +01:00
Lioncash
4bb286ac23
A32: Implement ASIMD VPADD (integer)
2020-06-20 21:22:14 +01:00
Lioncash
1ffeeeb6a2
A32: Implement ASIMD VMAX/VMIN (integer)
2020-06-20 21:20:47 +01:00
Lioncash
945b757b6c
A32: Implement ASIMD VMLA/VMLS (integer)
2020-06-20 21:20:21 +01:00
MerryMage
715db8381f
A32: Implement ASIMD VMUL (scalar)
2020-06-20 20:34:08 +01:00
MerryMage
b0beecdd41
A32: Implement ASIMD VTBL
2020-06-20 19:25:14 +01:00
MerryMage
28f27bc19d
A32: Implement ASIMD VEXT
2020-06-20 19:05:14 +01:00
MerryMage
e8c460c167
A32: Implement ASIMD VDUP (ARM core register)
2020-06-20 16:02:43 +01:00
MerryMage
15ee562dd0
decoder/asimd: Add misc data-processing instructions
2020-06-20 15:39:00 +01:00
MerryMage
92cb4a5a34
A32: Implement ASIMD VRSQRTE
2020-06-20 15:13:22 +01:00
MerryMage
6f59c2cd8e
A32: Implement ASIMD VRECPE
2020-06-20 15:07:06 +01:00
MerryMage
d3dc50d718
A32: Implement ASIMD VRSQRTS
2020-06-20 15:06:06 +01:00
MerryMage
8f506c80c3
A32: Implement ASIMD VRECPS
2020-06-20 14:39:05 +01:00
MerryMage
9eef4f7471
A32: Implement ASIMD VMLA, VMLS (floating-point)
2020-06-20 14:31:06 +01:00
MerryMage
60f6e729ac
A32: Implement ASIMD VABD (floating-point)
2020-06-20 14:25:04 +01:00
MerryMage
f58e247ef3
A32: Implement ASIMD VPADD (floating-point)
2020-06-20 14:25:04 +01:00
MerryMage
e006f0a205
A32: Implement ASIMD VSUB (floating-point)
2020-06-20 14:20:28 +01:00
MerryMage
4c939b9d0a
A32: Implement ASIMD VADD (floating-point)
2020-06-20 14:20:28 +01:00
MerryMage
5ec8e48593
A32: Implement ASIMD VMUL (floating-point)
...
* Also add fpcr_controlled arguments to FPVectorMul IR instruction
* Merge ASIMD floating-point instruction implementations
2020-06-20 14:20:28 +01:00
MerryMage
bb4f3aa407
A32: Implement ASIMD VMAX, VMIN (floating-point)
2020-06-20 03:21:07 +01:00
Lioncash
8d067d5d60
A32: Implement ASIMD VMUL (integer and polynomial)
2020-06-20 00:53:56 +01:00
Lioncash
ed6ca58058
A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero
...
Fairly self-explanatory, we can leverage the existing IR functions for
the purpose of these instructions.
In the integer case, we can just insert function pointers
into an array and index it, given all comparison primitives exist
already for the integer side of things.
2020-06-20 00:50:40 +01:00
MerryMage
656419286c
ir: Add fpcr_controlled argument to FPVector{Equal,Greater,GreaterEqual}
2020-06-20 00:50:40 +01:00
MerryMage
d3664b03fe
ir_emitter: Default fpcr_controlled arguments to true
2020-06-19 22:51:23 +01:00
Lioncash
794440cf8d
A32: Implement ASIMD VRSHL
2020-06-19 21:27:48 +01:00
