MerryMage
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bfd65bedfe
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A64: Implement DSB, DMB
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5edd623b9d
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Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
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Lioncash
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a9153218bd
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A64: Implement NOT (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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aed4fd3ec3
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A64: Implement FADD (vector), vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5f77ab28ee
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A64: Implement SSHLL, SSHLL2
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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3738043e58
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A64: Implement DUP (element), vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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ce7628b6b5
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load_store_multiple_structures: Improve IR codegen for selem == 1 case
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f1cb5581c9
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A64: Implement FSUB (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
6c9b4f0114
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A64: Implement CNT
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
1dd2b33b87
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A64: Implement MLS (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5eac3abf52
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A64: Implement MLA (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
3afd2fcbad
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A64: Implement MUL (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e7041d7196
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A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
a455ff70c9
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decoder/a64: Don't rearrange unrelated decoders
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
faeb77e8c4
|
A64: Implement SUB (vector)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bd106c3ae7
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A64: Implement SIMD instruction SSRA, vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
f58aba9871
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A64: Implement SIMD instruction SSHR, vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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653c82d8f0
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impl: Improve Vpart setter
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
e858ce0b35
|
A64: Implement SIMD instructions XTN, XTN2
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
3f93c77ace
|
A64: Implement SIMD instruction USRA, vector variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
fb9d20f27f
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A64: Implement SIMD instruction USHR, vector variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
7ff280827b
|
A64: Implement SIMD instructions USHLL, USHLL2
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
d3a4e1efe2
|
IR: Vector instructions now take esize argument in emitter
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
1d0cd95b23
|
A64: Implement SIMD instruction SHL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
15e8231f24
|
opcodes: Sort vector IR opcodes alphabetically
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2020-04-22 20:46:13 +01:00 |
|
FernandoS27
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15871910af
|
Implemented BSL, BIC, BIT and BIF vector instructions
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
4e33629b0e
|
A64: Move SDIV and UDIV out of data_processing_multiply.cpp
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2020-04-22 20:46:13 +01:00 |
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Lioncash
|
35a29a9665
|
A64: Implement ZIP1
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2020-04-22 20:46:13 +01:00 |
|
FernandoS27
|
586854117b
|
Implemented UMULH and SMULH instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
1a7b7b541a
|
A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
8ab7d8175c
|
impl: Add AdvSIMDExpandImm
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ea69cb4474
|
A64: Implement SUB (vector), scalar variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4c5871d5d5
|
A64: Implement ADD (vector), scalar variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
2a0850c068
|
A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7b33772ac6
|
A64: Implement BIC (vector, register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
eb5591859c
|
A64: Implement FMOV (general)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
dd88cee15a
|
translate/impl: Add Vpart
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
cc9efd13c9
|
A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
81713c2b77
|
A64: Implement FCCMPE
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ef906dbbfa
|
A64: Implement FCCMP
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
aac5af50e2
|
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
2ee39d6b36
|
A64: Implement FMOV (register)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
b02b861242
|
A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
5a65313236
|
A64: Implement CCMP (immediate)
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ab4664de61
|
A64: Implement CCMN (immediate)
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
a6c6539109
|
A64: Implement CCMP (register)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
c5033b5dda
|
A64: Implement CCMN (register)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4491746eae
|
A64: Implement FNEG
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
db958061a3
|
A64: Implement FABS
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
8765b421b7
|
A64: Implement FCSEL
|
2020-04-22 20:46:13 +01:00 |
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