MerryMage
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dd88cee15a
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translate/impl: Add Vpart
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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cc9efd13c9
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A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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81713c2b77
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A64: Implement FCCMPE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ef906dbbfa
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A64: Implement FCCMP
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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aac5af50e2
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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2ee39d6b36
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A64: Implement FMOV (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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b02b861242
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A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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5a65313236
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A64: Implement CCMP (immediate)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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ab4664de61
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A64: Implement CCMN (immediate)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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a6c6539109
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A64: Implement CCMP (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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c5033b5dda
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A64: Implement CCMN (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4491746eae
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A64: Implement FNEG
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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db958061a3
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A64: Implement FABS
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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8765b421b7
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A64: Implement FCSEL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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7e82d8eede
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A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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2409e5d082
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A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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56bc7825ef
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A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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40614202e7
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A64: Implement AESD
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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ccef85dbb7
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A64: Implement AESE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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0bb4474fb9
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A64: Implement INS (general)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d13704fdef
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A64: Implement INS (element)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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0642d49919
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A64: Implement SMOV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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5297027ebe
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A64: Implement UMOV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1fb0957aa3
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A64: Implement FCVT
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4be55b8b84
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A64: Implement FMOV (scalar, immediate)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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a07c05ea51
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A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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93fcbdf1e2
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A64: Implement FCMP, FCMPE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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99d8ebe4d5
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A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ed2bedec43
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A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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a5c4fbc783
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A64: Implement AESIMC and AESMC
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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af1384d700
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A64: Implement CRC32
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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7ffbebf290
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A64: Implement CRC32C
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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d7044bc751
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assert: Use fmt in ASSERT_MSG
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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52268298a8
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a64_emit_x64: Perform RSB predictions
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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7734cf1050
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A64: Implement EXTR
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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88ae7fce52
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A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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b513b2ef05
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IR: Implement IR instructions A64{Get,Set}S
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2020-04-22 20:44:38 +01:00 |
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Lioncash
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67443efb62
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
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2020-04-22 20:44:38 +01:00 |
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Lioncash
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7abd673a49
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A64: Zero upper 64 bits in ORN if using the 64-bit variant
Resolves a TODO
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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ba3d6da0c8
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load_store_register_unprivileged: bug: LDTRSW
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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75756137c6
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A64: Implement CMEQ (register, vector)
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2020-04-22 20:44:38 +01:00 |
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Fernando Sahmkow
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e0c12ec2ad
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A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
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2020-04-22 20:44:38 +01:00 |
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James Rowe
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589ad7232f
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Fixup: Xn|SP are 64 bit addresses encoded in the Rn field
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2020-04-22 20:44:38 +01:00 |
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James Rowe
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ae880d8391
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A64: Fix bugs and address review comments
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2020-04-22 20:44:38 +01:00 |
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James Rowe
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3aeb7ca50c
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Add missing returns
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2020-04-22 20:44:38 +01:00 |
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James Rowe
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41e6e659c5
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A64: Implement Load/Store register (unprivileged)
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2020-04-22 20:44:37 +01:00 |
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FernandoS27
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ab84524806
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Implemented SDIV and UDIV instructions
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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6033b05ca6
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A64: Implement LDR/STR (immediate, SIMD&FP)
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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e1df7ae621
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IR: Add IR instructions A64Memory{Read,Write}128
This implementation only works on macOS and Linux.
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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3caf192f60
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A64: Implement DUP (general)
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2020-04-22 20:44:37 +01:00 |
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