Lioncash
|
a1d6a86e8c
|
A64: Implement ADDV
|
2020-04-22 20:46:19 +01:00 |
|
MerryMage
|
d875c08ebf
|
fp: Extract common RoundingMode enum
|
2020-04-22 20:46:18 +01:00 |
|
MerryMage
|
436ca80bcd
|
Merge branch 'global_monitor'
|
2020-04-22 20:46:18 +01:00 |
|
MerryMage
|
57f7c7e1b0
|
Implement global exclusive monitor
|
2020-04-22 20:46:18 +01:00 |
|
MerryMage
|
2fc6b33829
|
CMakeLists: Add missing files
|
2020-04-22 20:46:18 +01:00 |
|
Lioncash
|
593eca7fb1
|
A64: Implement load/store single structure instructions
Implements LD{1, 2, 3, 4}, LD{1, 2, 3, 4}R, and ST{1, 2, 3, 4} single
structure variants.
|
2020-04-22 20:46:18 +01:00 |
|
MerryMage
|
8c90fcf58e
|
IR: Implement FPMulAdd
|
2020-04-22 20:46:18 +01:00 |
|
Lioncash
|
b312d28295
|
ir: Add an opcode for doing an SM4 lookup table query
|
2020-04-22 20:46:17 +01:00 |
|
MerryMage
|
a86d4093cd
|
A64: Implement MLA (by element)
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
870e418b0b
|
A64: Implement SHL (scalar)
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
769373b3ed
|
A64: Implement SM3TT1A
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
cf81f04ed3
|
A64: Implement RAX1
|
2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
78a047f0f9
|
A64: Implement EXT
|
2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
8bba37089e
|
A64: Implement UADDW
|
2020-04-22 20:46:15 +01:00 |
|
Lioncash
|
94f0fba16b
|
A64: Implement SHA1H
This is a fairly trivial instruction it's essentially:
result = ROL(data, 30);
|
2020-04-22 20:46:15 +01:00 |
|
Lioncash
|
6177c2c63d
|
CMakeLists: Add fp_util, macro_util and math_util headers
Allows the headers to show up within IDEs
|
2020-04-22 20:46:15 +01:00 |
|
Lioncash
|
7a66224d9a
|
A64: Implement EOR3 and BCAX
|
2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
fd8f4c1195
|
A64: Implement UCVTF (vector, integer), scalar variant
|
2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
be57608353
|
A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
|
2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
bd2b415850
|
A64: Implement ADDP (scalar)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e97581d063
|
fuzz_with_unicorn: Print AArch64 disassembly
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5edd623b9d
|
Implement DC instructions
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b9cd345ddc
|
IR: Implement FPVectorSub
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f378d2ef1b
|
Forward declare IR::Opcode and IR::Type where possible
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e858ce0b35
|
A64: Implement SIMD instructions XTN, XTN2
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1d0cd95b23
|
A64: Implement SIMD instruction SHL
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
afe16fa0f3
|
cast_util: Add BitCast and BitCastPointee
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
35a29a9665
|
A64: Implement ZIP1
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1a7b7b541a
|
A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4c5871d5d5
|
A64: Implement ADD (vector), scalar variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ef906dbbfa
|
A64: Implement FCCMP
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
b02b861242
|
A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
c5033b5dda
|
A64: Implement CCMN (register)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
8765b421b7
|
A64: Implement FCSEL
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
2409e5d082
|
A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
56bc7825ef
|
A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4be55b8b84
|
A64: Implement FMOV (scalar, immediate)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
93fcbdf1e2
|
A64: Implement FCMP, FCMPE
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
99d8ebe4d5
|
A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ed2bedec43
|
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
a5c4fbc783
|
A64: Implement AESIMC and AESMC
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ab9b5fb8aa
|
Common: Relocate common bits of CRC32
Allows the algorithm to be used in any other potential backend.
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
bafb39ebc5
|
A64: Add Disassemble method
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
7ffbebf290
|
A64: Implement CRC32C
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
98ec9c5f90
|
A32: Change UserCallbacks to be similar to A64's interface
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
6fc228f7fd
|
ir_opt: Add A64 Get/Set Elimination Pass
|
2020-04-22 20:46:12 +01:00 |
|
James Rowe
|
41e6e659c5
|
A64: Implement Load/Store register (unprivileged)
|
2020-04-22 20:44:37 +01:00 |
|
Lioncash
|
5281d3c6d5
|
CMakeLists: Add opcodes.inc to the source file list
Allows the file to show up nicely within IDEs
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
30936f5e94
|
travis: Test with disabled CPU feature detection
Ensure that fallbacks are working correctly.
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
3caf192f60
|
A64: Implement DUP (general)
|
2020-04-22 20:44:37 +01:00 |
|