Lioncash
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6ad1bce5e0
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A64: Implement REV16 (vector)
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2020-04-22 20:46:15 +01:00 |
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Lioncash
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7a66224d9a
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A64: Implement EOR3 and BCAX
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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be5047c7c2
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impl: Update PC when raising exception
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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49cc6d7fad
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A64: Implement FDIV (vector)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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fd075d8d68
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system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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c832cec96d
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Correct FPSR and FPCR
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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147284427b
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A64: Implement USHL
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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fd8f4c1195
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A64: Implement UCVTF (vector, integer), scalar variant
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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be57608353
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A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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e4697b1676
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A64: Implement system register TPIDR_EL0
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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e3da92024e
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A64: Implement system registers FPCR and FPSR
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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9e4e4e9c1d
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A64: Implement system register CNTPCT_EL0
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1e15283d00
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A64: Implement system register CTR_EL0
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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58fbb3ff1b
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A64: Implement NEG (vector)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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710d09471b
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IR: Add IR instruction ZeroVector
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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0575e7421b
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A64: Implement FMINNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1c9804ea07
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A64: Implement FMAXNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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bd2b415850
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A64: Implement ADDP (scalar)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9df3793af0
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A64: Implement DUP (element), scalar variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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2080a51f41
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A64: Implement FMAX (scalar), FMIN (scalar)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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0e157b0198
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A64: Implement FSQRT (scalar)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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01c1e9017e
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T32: Add initial decoder list
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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ccf7df057b
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simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8cebb87d0d
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A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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7f68d556ab
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decoder/a64: Rearrange SIMD two-register misc decoders
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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d5af052f06
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A64: Implement CMGE (register)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9d85991906
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A64: Implement CMHI, CMHS
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e2b9b7c5b0
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IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned}
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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0df6725f73
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A64: Implement SMAX, SMIN, UMAX, UMIN
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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47c0ad0fc8
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IR: Implement Vector{Max,Min}{Signed,Unsigned}
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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adb7f5f86f
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A64: Implement CMGT (register)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f4775910f5
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IR: Implement VectorGreaterSigned
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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1f5b3bca43
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Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8698f057d0
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A64: Implement STXP, STLXP, LDXP, LDAXP
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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2a6619d59c
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A64: Implement CLREX
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b7a2c1a7df
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8756487554
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A64: Partially implement MRS
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bfd65bedfe
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A64: Implement DSB, DMB
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5edd623b9d
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Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
|
Lioncash
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a9153218bd
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A64: Implement NOT (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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2cb0a699ba
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IR: Implement FPMax, FPMin
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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aed4fd3ec3
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A64: Implement FADD (vector), vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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98c8e7d1af
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IR: Implement FPVectorAdd
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5f77ab28ee
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A64: Implement SSHLL, SSHLL2
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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eae518a338
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IR: Implement VectorSignExtend
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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3738043e58
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A64: Implement DUP (element), vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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ce7628b6b5
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load_store_multiple_structures: Improve IR codegen for selem == 1 case
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f1cb5581c9
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A64: Implement FSUB (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b9cd345ddc
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IR: Implement FPVectorSub
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
f378d2ef1b
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Forward declare IR::Opcode and IR::Type where possible
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2020-04-22 20:46:14 +01:00 |
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