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  • e268b110f0 simd_sha512: Simplify RAX1 Lioncash 2018-04-12 08:03:46 -0400
  • 20d2491267 A64: Implement SM3PARTW2 Lioncash 2018-04-10 14:24:04 -0400
  • e1b662e90c ir: Add helper functions for vector rotation Lioncash 2018-04-10 14:36:35 -0400
  • 8a60a63a8b A64: Implement SM3TT2B Lioncash 2018-04-10 13:48:24 -0400
  • b3d4c02098 A64: Implement SM3TT2A Lioncash 2018-04-10 13:36:25 -0400
  • 7fbccabd81 A64: Implement SM3TT1B Lioncash 2018-04-10 12:16:10 -0400
  • 769373b3ed A64: Implement SM3TT1A Lioncash 2018-04-08 20:49:43 -0400
  • 2d269fdcc7 simd_shift_by_immediate: Merge signed/unsigned helper functions Lioncash 2018-04-08 23:49:30 -0400
  • d5461be6b4 A64: Implement SM3SS1 Lioncash 2018-04-08 00:58:47 -0400
  • 2db032ac83 A64: Implement SRI (vector) Lioncash 2018-04-07 23:54:14 -0400
  • 11005cfe26 A64: Implement SLI (vector) Lioncash 2018-04-07 23:31:19 -0400
  • e3d9bf55e7 A64: Implement SRSRA (vector) Lioncash 2018-04-07 23:14:20 -0400
  • bc6016cad7 A64: Implement SRSHR (vector) Lioncash 2018-04-07 21:04:29 -0400
  • 6c9c829a08 imm: Add additional bit position checks to Imm::Bits MerryMage 2018-04-08 10:42:23 +0100
  • be907a61f7 math_util: rvalue references for std::forward MerryMage 2018-04-08 10:37:11 +0100
  • a2f8cdf0a3 A64: Implement SSUBL/SSUBL2 Lioncash 2018-04-05 09:43:38 -0400
  • d456fb85c8 A64: Implement SADDL/SADDL2 Lioncash 2018-04-05 09:41:59 -0400
  • 5c9e7f328d A64: Implement USUBL/USUBL2 Lioncash 2018-04-05 09:35:57 -0400
  • 88d70e3b8a A64: Implement UADDL/UADDL2 Lioncash 2018-04-05 09:28:50 -0400
  • 4b3d70de5f simd_shift_by_immediate: Factor out common code in shift instructions Lioncash 2018-04-04 09:38:45 -0400
  • 56803f5203 A64: Implement URSRA (vector) Lioncash 2018-04-04 08:46:56 -0400
  • 8afdf4b23d A64: Implement URSHR (vector) Lioncash 2018-04-04 08:36:02 -0400
  • 16613ee066 A64: Implement RSHRN/RSHRN2 Lioncash 2018-04-03 16:04:17 -0400
  • 937990fd2a A64: Implement SHRN/SHRN2 Lioncash 2018-04-03 13:24:06 -0400
  • 80e005e5b5 A64/translate: Amend I() to also handle u8 and u16 immediates Lioncash 2018-04-03 18:23:46 -0400
  • c490a45af6 fuzz_with_unicorn: Correct GenRandomInst MerryMage 2018-04-04 11:04:19 +0100
  • 7969871aa3 A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated MerryMage 2018-04-04 10:28:52 +0100
  • 5c95e28ed0 A64: Implement ZIP2 MerryMage 2018-04-03 10:10:53 +0100
  • ce5ad240fa travis: Enable DYNARMIC_USE_LLVM MerryMage 2018-04-03 22:11:40 +0100
  • 871aefb9a0 decoder/a64: Tweak ordering algorithm MerryMage 2018-04-04 09:03:48 +0100
  • 575590d18d ir_emitter: Remove overloads MerryMage 2018-04-03 22:26:29 +0100
  • 83ff7a43d1 A64: Implement RBIT (vector) Lioncash 2018-04-03 10:47:39 -0400
  • 64b1f2d468 ir: Add opcode for reversing bits in a vector Lioncash 2018-04-03 08:46:01 -0400
  • 9de60b60bb A64/translate: Amend instruction prototypes erroneously marked as taking Reg Lioncash 2018-04-03 12:02:54 -0400
  • cf81f04ed3 A64: Implement RAX1 Lioncash 2018-04-03 08:12:13 -0400
  • 7371e63a7b a64_get_set_elimination_pass: Make TrackingType enum an enum class Lioncash 2018-04-03 00:49:50 -0400
  • 7bcb1c115a A64: Implement ABS (vector) Lioncash 2018-04-02 17:11:56 -0400
  • e33dcce14a ir: Add opcodes for performing vector absolute values Lioncash 2018-04-02 16:27:04 -0400
  • 84d49309b9 A64: Implement USUBW/USUBW2 Lioncash 2018-04-02 19:46:20 -0400
  • e20fce6b5a A64: Implement SSUBW/SSUBW2 Lioncash 2018-04-02 20:13:04 -0400
  • 00af6eeab9 A64: Implement SADDW/SADDW2 Lioncash 2018-04-02 20:10:22 -0400
  • 78a047f0f9 A64: Implement EXT MerryMage 2018-04-02 22:10:28 +0100
  • 3472f371df IR: Implement VectorExtract, VectorExtractLower IR instructions MerryMage 2018-04-02 21:52:46 +0100
  • 8bba37089e A64: Implement UADDW MerryMage 2018-04-02 21:15:51 +0100
  • 5c47f03888 A64: Implement FMUL (vector) MerryMage 2018-04-02 21:02:57 +0100
  • a6e264c2dd A64: Implement UABA Lioncash 2018-04-02 11:39:40 -0400
  • c2e7364d3e A64: Implement UABD Lioncash 2018-04-02 11:25:26 -0400
  • ad5cf584ce ir: Add opcodes for performing vector unsigned absolute differences Lioncash 2018-04-01 14:21:14 -0400
  • 7780af56e3 ir_emitter: Make immediate member functions const qualified Lioncash 2018-04-02 13:58:35 -0400
  • 701f43d61e IR: Add opcodes for interleaving upper-order bytes/halfwords/words/doublewords Lioncash 2018-03-29 16:11:14 -0400
  • 94f0fba16b A64: Implement SHA1H Lioncash 2018-03-29 16:41:42 -0400
  • 3985f7bf84 emit_x64_data_processing: Deduplicate some code in zero-extension functions Lioncash 2018-03-29 14:56:31 -0400
  • 40ec25356b A64: NOP immediate variant of PRFM Lioncash 2018-03-29 15:16:23 -0400
  • e7b60189b3 abi: Missing includes' MerryMage 2018-03-29 12:46:29 +0100
  • cdc5c3ad95 emit_x64_floating_point: Near jump instead of short jump in FPMinNumberic{32,64} MerryMage 2018-03-29 12:45:33 +0100
  • 73b9e4b276 A64: system: Use an enum class for MRS/MSR register encodings Lioncash 2018-03-28 11:14:34 -0400
  • df4ee0f51e emit_X64_floating_point: Near jmp to end instead of short jmp MerryMage 2018-03-27 08:21:18 +0100
  • b8d5765f9b emit_x64_vector: Fix typo in VectorShuffleImpl Lioncash 2018-03-23 14:44:10 -0400
  • 586b00d11d A64: Implement REV64 Lioncash 2018-03-23 12:01:42 -0400
  • ade595e377 bit_util: Do nothing in RotateRight if the rotation amount is zero Lioncash 2018-03-21 13:51:47 -0400
  • 9128988dc3 A64: Implement REV32 (vector) Lioncash 2018-03-17 21:05:30 -0400
  • 6b0010c940 ir: Add IR opcodes for emitting vector shuffles Lioncash 2018-03-17 20:32:07 -0400
  • eb2d28d2b1 emit_x64_vector_floating_point: Fix out of bounds array access in EmitVectorOperation64 Lioncash 2018-03-21 11:35:21 -0400
  • 6ad1bce5e0 A64: Implement REV16 (vector) Lioncash 2018-03-15 16:59:48 -0400
  • 6177c2c63d CMakeLists: Add fp_util, macro_util and math_util headers Lioncash 2018-03-12 14:52:27 -0400
  • 7a66224d9a A64: Implement EOR3 and BCAX Lioncash 2018-01-25 21:28:03 -0500
  • bc4bde1fbd travis: Use yuzu's unicorn fork Lioncash 2018-03-12 12:04:00 -0400
  • 8e28bea0ac externals: Update catch to v2.2.1 Lioncash 2018-03-12 13:58:58 -0400
  • be5047c7c2 impl: Update PC when raising exception MerryMage 2018-02-21 21:02:42 +0000
  • 49cc6d7fad A64: Implement FDIV (vector) MerryMage 2018-02-21 14:07:31 +0000
  • fd075d8d68 system: Raise exception for YIELD, WFE, WFI, SEV, SEVL MerryMage 2018-01-26 18:50:41 +0000
  • c832cec96d Correct FPSR and FPCR MerryMage 2018-02-20 20:29:15 +0000
  • 147284427b A64: Implement USHL MerryMage 2018-02-20 19:48:15 +0000
  • fd8f4c1195 A64: Implement UCVTF (vector, integer), scalar variant MerryMage 2018-02-20 19:04:56 +0000
  • be57608353 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) MerryMage 2018-02-20 18:45:28 +0000
  • e4697b1676 A64: Implement system register TPIDR_EL0 MerryMage 2018-02-20 17:56:20 +0000
  • e3da92024e A64: Implement system registers FPCR and FPSR MerryMage 2018-02-20 17:38:29 +0000
  • 9e4e4e9c1d A64: Implement system register CNTPCT_EL0 MerryMage 2018-02-20 16:54:10 +0000
  • 1e15283d00 A64: Implement system register CTR_EL0 MerryMage 2018-02-20 16:44:13 +0000
  • 58fbb3ff1b A64: Implement NEG (vector) MerryMage 2018-02-20 15:38:45 +0000
  • 710d09471b IR: Add IR instruction ZeroVector MerryMage 2018-02-20 15:38:32 +0000
  • 2721bb5ace emit_x64_floating_point: Add maybe_unused to preprocess parameter MerryMage 2018-02-20 15:40:37 +0000
  • 0575e7421b A64: Implement FMINNM (scalar) MerryMage 2018-02-20 14:08:46 +0000
  • 1c9804ea07 A64: Implement FMAXNM (scalar) MerryMage 2018-02-20 14:05:14 +0000
  • 1dfce0894d constant_pool: Add frame parameter MerryMage 2018-02-20 14:04:11 +0000
  • bd2b415850 A64: Implement ADDP (scalar) MerryMage 2018-02-18 23:55:38 +0000
  • 84f1c9b7f4 reg_alloc: Only exchange GPRs MerryMage 2018-02-18 23:24:15 +0000
  • 9df3793af0 A64: Implement DUP (element), scalar variant MerryMage 2018-02-18 18:58:01 +0000
  • 6541ec064d emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0 MerryMage 2018-02-18 15:08:32 +0000
  • 2080a51f41 A64: Implement FMAX (scalar), FMIN (scalar) MerryMage 2018-02-11 16:44:02 +0000
  • 44a5b57f2a fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect MerryMage 2018-02-18 13:47:41 +0000
  • eaa1fd36a7 travis: Switch unicorn repository MerryMage 2018-02-18 13:21:29 +0000
  • 7c193485e1 a64/config: Allow NaN emulation accuracy to be set MerryMage 2018-02-18 13:04:45 +0000
  • a3df46a75a a64_emit_x64: Add conf to A64EmitContext MerryMage 2018-02-18 13:00:41 +0000
  • 1311f67b4a fuzz_with_unicorn: Explicitly test floating point instructions MerryMage 2018-02-18 12:37:55 +0000
  • 0e157b0198 A64: Implement FSQRT (scalar) MerryMage 2018-02-18 12:54:51 +0000
  • 07520f32c3 backend_x64: Accurately handle NaNs MerryMage 2018-02-18 12:54:39 +0000
  • e97581d063 fuzz_with_unicorn: Print AArch64 disassembly MerryMage 2018-02-18 11:20:43 +0000
  • 01c1e9017e T32: Add initial decoder list MerryMage 2018-02-14 19:29:19 +0000
  • ccf7df057b simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector) MerryMage 2018-02-13 19:01:47 +0000