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2232 commits

Author SHA1 Message Date
Lioncash
fb1405157b thumb32: Implement UMAAL 2021-02-07 17:45:00 -05:00
Lioncash
f9bbc25e29 thumb32: Implement SMLSLD{X} 2021-02-07 17:42:44 -05:00
Lioncash
fe3deb1831 thumb32: Implement SMLALD{X} 2021-02-07 17:40:36 -05:00
Lioncash
87cb771bd2 thumb32: Implement SMLALXY 2021-02-07 17:37:26 -05:00
Lioncash
8320c56a6e thumb32: Implement UMLAL 2021-02-07 17:34:05 -05:00
Lioncash
5859105a61 thumb32: Implement SMLAL 2021-02-07 17:32:11 -05:00
Lioncash
28108c7924 thumb32: Implement UMULL 2021-02-07 17:29:20 -05:00
Lioncash
6cf47e0ce0 thumb32: Implement SMULL 2021-02-07 17:22:43 -05:00
merry
7290ae1273
Merge pull request #573 from lioncash/multiply2 
thumb32: Implement the rest of the thumb-2 multiply category instructions
 2021-02-07 21:04:42 +00:00
MerryMage
f77b0e2fbe A32/thumb16: Implement IT instruction 2021-02-07 20:41:48 +00:00
MerryMage
97d8b50c25 A32: Ensure existing thumb code is ITState-correct 2021-02-07 20:41:48 +00:00
MerryMage
68bd9547c5 fuzz_arm: Correctly print thumb instruction listing 2021-02-07 20:41:48 +00:00
MerryMage
62003a2d89 A32/ir_emitter: Implement UpdateUpperLocationDescriptor 2021-02-07 20:41:48 +00:00
MerryMage
f229a68aed a32_emit_x64: Update upper_location_descriptor in BXWritePC based on final location 2021-02-07 20:41:48 +00:00
MerryMage
714b0b9a8b A32/translate: Factor conditional state handling out 2021-02-07 20:41:48 +00:00
Lioncash
b58cd3a996 thumb32: Implement SMLAWY 2021-02-07 13:34:56 -05:00
Lioncash
96895d2eb5 thumb32: Implement SMULWY 2021-02-07 13:32:39 -05:00
Lioncash
8a22bdff43 thumb32: Implement SMLSD{X} 2021-02-07 13:29:20 -05:00
Lioncash
ef3b77f8ae thumb32: Implement SMLAD{X} 2021-02-07 13:26:53 -05:00
Lioncash
53f1a52be9 thumb32: Implement SMMLS{R} 2021-02-07 13:23:21 -05:00
Lioncash
0c542777b0 thumb32: Implement SMMLA{R} 2021-02-07 13:14:47 -05:00
Lioncash
b6add0ddf4 thumb32: Implement SMMUL{R} 2021-02-07 13:11:25 -05:00
Lioncash
44f4f437a7 thumb32: Implement SMUSD 2021-02-07 13:07:38 -05:00
Lioncash
4d9a7308ac thumb32: Implement SMUAD 2021-02-07 13:04:18 -05:00
Lioncash
1e06231575 thumb32: Implement SMLAXY 2021-02-07 12:39:12 -05:00
Lioncash
1cd10e3214 thumb32: Implement SMULXY 2021-02-07 12:27:40 -05:00
MerryMage
1e29ef8b0e A32/location_descriptor: Implement SetIT 2021-02-07 14:18:03 +00:00
MerryMage
5e75bd41a4 ITState: Handle not-in-IT-block case in Cond 2021-02-07 14:17:46 +00:00
MerryMage
946dbb5818 ITSTate: Correct ITState::Advance 2021-02-07 13:21:45 +00:00
MerryMage
1c5f6882f0 A32/translate_thumb: Correct IsThumb16 2021-02-07 12:18:45 +00:00
MerryMage
7e5ae6076a A32: Add arch_version option 2021-02-07 12:13:14 +00:00
Lioncash
50d81f95e5 thumb32: Implement USADA8 2021-02-07 09:57:34 +00:00
Lioncash
ed453aa52d thumb32: Implement USAD8 2021-02-07 09:57:34 +00:00
Lioncash
b07fab604f thumb32: Implement MLS 2021-02-07 09:57:34 +00:00
Lioncash
cf5058bccb thumb32: Implement MLA 2021-02-07 09:57:34 +00:00
Lioncash
153d87c843 thumb32: Implement MUL 2021-02-07 09:57:34 +00:00
MerryMage
8b612edb75 translate_thumb: Fix bug in TranslateSingleThumbInstruction 2021-02-06 21:26:44 +00:00
MerryMage
aa89418e8b bit_util: Add SwapHalves32 2021-02-06 21:26:44 +00:00
MerryMage
fa1b9545fd bit_util: Rename Swap{16,32,64} to SwapBytes{16,32,64} 2021-02-06 21:26:44 +00:00
MerryMage
39644d69ee A32/decode: Split thumb32 2021-02-06 21:26:42 +00:00
MerryMage
6d0a049fb2 A32/decode: Split thumb16 2021-02-06 21:25:24 +00:00
MerryMage
ac9e1ccb1c A32/thumb16: Fix bug in CBZ/CBNZ 2021-02-06 21:25:24 +00:00
Lioncash
23619c8c6a thumb32: Implement SHSUB8/UHSUB8 2021-02-01 17:50:46 -05:00
Lioncash
9d2570470e thumb32: Implement SHADD8/UHADD8 2021-02-01 17:50:46 -05:00
Lioncash
afad76078d thumb32: Implement SHSUB16/UHSUB16 2021-02-01 17:50:46 -05:00
Lioncash
51b7c32d02 thumb32: Implement SHSAX/UHSAX 2021-02-01 17:50:46 -05:00
Lioncash
f0a219fcd0 thumb32: Implement SHASX/UHASX 2021-02-01 17:50:46 -05:00
Lioncash
94f8efbb03 thumb32: Implement SHADD16/UHADD16 2021-02-01 17:50:46 -05:00
Lioncash
aa49b0db89 thumb32: Implement QSUB8/UQSUB8 2021-02-01 17:50:46 -05:00
Lioncash
874ab6a7b6 thumb32: Implement QADD8/UQADD8 2021-02-01 17:50:46 -05:00
Lioncash
d923fb24c6 thumb32: Implement QSUB16/UQSUB16 2021-02-01 17:50:46 -05:00
Lioncash
416fe26df0 thumb32: Implement QSAX/UQSAX 2021-02-01 17:50:14 -05:00
Lioncash
ad7c8bd042 thumb32: Implement QASX/UQASX 2021-02-01 17:31:30 -05:00
Lioncash
f52b8f924c thumb32: Implement QADD16/UQADD16 2021-02-01 17:31:30 -05:00
Lioncash
6f593da41b thumb32: Implement SSUB8/USUB8 2021-02-01 17:31:27 -05:00
Lioncash
271354ee95 thumb32: Implement SADD8/UADD8 2021-02-01 16:44:11 -05:00
Lioncash
8f42fd5c0e thumb32: Implement SSUB16/USUB16 2021-02-01 16:41:02 -05:00
Lioncash
0e28c63456 thumb32: Implement SSAX/USAX 2021-02-01 16:36:18 -05:00
Lioncash
21e404d3ab thumb32: Implement SASX/UASX 2021-02-01 16:31:25 -05:00
Lioncash
d529417875 thumb32: Implement SADD16/UADD16 2021-02-01 16:19:33 -05:00
merry
0e26e8a531
Merge pull request #569 from lioncash/t32-misc 
thumb32: Implement miscellaneous category instructions
 2021-02-01 21:06:36 +00:00
Lioncash
36fc596a51 thumb32: Implement QADD 2021-02-01 15:44:09 -05:00
Lioncash
cd6e4c7afd thumb32: Implement QSUB 2021-02-01 15:42:14 -05:00
Lioncash
65365ad2a3 thumb32: Implement QDADD 2021-02-01 15:39:39 -05:00
Lioncash
d96c8c662b thumb32: Implement QDSUB 2021-02-01 15:35:09 -05:00
Lioncash
c60cf921ee thumb32: Implement REV 2021-02-01 15:30:40 -05:00
Lioncash
0304dc7ce4 thumb32: Implement REV16 2021-02-01 15:27:31 -05:00
Lioncash
cee31c5274 thumb32: Implement RBIT 2021-02-01 15:20:24 -05:00
Lioncash
e2bc7eeb93 thumb32: Implement REVSH 2021-02-01 15:16:53 -05:00
MerryMage
e01583abba A64/system: Reorder fields of SystemRegisterEncoding 
Matches manual, which allows for easier verification of correctness.
 2021-02-01 20:01:39 +00:00
Lioncash
1ad99bb9b5 thumb32: Implement SEL 2021-02-01 15:01:21 -05:00
Lioncash
8d53048750 thumb32: Implement CLZ 
Also fleshes out the generator to allow for generating thumb32
instructions as well.
 2021-02-01 14:54:04 -05:00
MerryMage
f2345c1590 A64/system: Implement MSR/MRS for NZCV 2021-02-01 19:52:49 +00:00
bunnei
de389968eb A32: Add hook_isb option. 2021-01-28 20:47:39 -08:00
MerryMage
0f27368fda A64: Add hook_isb option 2021-01-26 23:41:21 +00:00
MerryMage
3806284cbe emit_x64{,_vector}_floating_point: Fix non-FMA execution 
Avoid repeated calls to GetArgumentInfo
 2021-01-02 20:40:32 +00:00
MerryMage
6023bcd8ad emit_x64_data_processing: Fix signed/unsigned warning 2021-01-02 20:12:48 +00:00
MerryMage
c15917b350 backend/x64: Add further Unsafe_InaccurateNaN locations 2021-01-02 20:12:48 +00:00
MerryMage
f9ccf91b94 Add Unsafe_InaccurateNaN optimization to all fma instructions 2021-01-02 17:22:50 +00:00
MerryMage
8c4463a0c1 emit_x64_data_processing: EmitSub: Use cmp where possible 2021-01-01 19:37:47 +00:00
MerryMage
e926f0b393 emit_x64_data_processing: Minor optimization for immediates in EmitSub 2021-01-01 13:35:01 +00:00
MerryMage
eeeafaf5fb Introduce Unsafe_InaccurateNaN 2021-01-01 07:18:05 +00:00
ReinUsesLisp
4a9a0d07f7 backend/{a32,a64}_emit_x64: Add config entry to mask page table pointers 
Add config entry to mask out the lower bits in page table pointers.
This is intended to allow users of Dynarmic to pack small integers
inside pointers and update the pair atomically without locks.
These lower bits can be masked out due to the expected alignment in
pointers inside the page table.

For the given usage, using AND on the pointer acts the same way as a
TEST instruction. That said when the mask value is zero, TEST is still
emitted to keep the same behavior.
 2020-12-29 19:16:46 +00:00
MerryMage
42059edca4 decoder_detail: Fix bit_position and one unused warnings in GetArgInfo 2020-12-28 23:34:23 +00:00
MerryMage
b47e5ea1e1 emit_x64_data_processing: Use BMI2 shifts where possible 2020-12-28 22:42:51 +00:00
ReinUsesLisp
ba6654b0e7 location_descriptor: Fix compare operator for single stepping 
Compare `single_stepping` with the other's value instead of comparing it
with the local value.
 2020-12-01 09:11:40 +00:00
Wunk
3e932ca55d
emit_x64_vector: Fix ArithmeticShiftRightByte zero_extend constant 
Should be shifting in _bytes_ of `0x80`. Not bits.
 2020-11-09 09:47:51 -08:00
Wunkolo
ec52922dae emit_x64_vector: Use explicit 64-bit mask constant 
Exchange `~0ull` with `0xFFFFFFFFFFFFFFFF` when generating
the `zero_extend` constant.
 2020-11-07 15:29:12 +00:00
Wunkolo
490160ef43 emit_x64_vector: GNFI implementation of ArithmeticShiftRightByte 
The bit-matrix is generated up-front and added to the constant-pool.
I'm using an embedded 64-bit broadcast here(m64bcst) which is the particular
EVEX encoded version of the instruction with AVX512VL+GNFI.

If it ever really matters, then we would ideally detect specific host
features like bare-GFNI and specific subsets of AVX512 and emit
the assembly based on that rather than by the entire Icelake uarch.
 2020-11-07 15:29:12 +00:00
Wunkolo
7df235aefb emit_x64_vector: GNFI implementation of EmitVectorLogicalShiftLeft8 
Same principle as EmitVectorLogicalShiftRight8. An 8x8 galois identity
matrix is bit-shfited to allow for arbitrary 8-bit-lane shifts.
 2020-11-07 15:29:12 +00:00
Wunkolo
5cc646ffed emit_x64_vector: GNFI implementation of EmitVectorLogicalShiftRight8 
Bitshifts of the GFNI identity matrix generates a new matrix that
applies lane-wise bitshifts as well. This allows for a fast
single-instruction implementation of a byte-lane bitshift.
 2020-11-07 15:29:12 +00:00
MerryMage
46f96904db decoder_detail: Add check for N==0 to GetArgInfo 2020-10-11 22:12:21 +01:00
Wunkolo
6bb49726f4 emit_x64_vector: GNFI+SSSE3 implementation of EmitVectorReverseBits 
Performs a full 128-bit bit-reversal using only two instructions.

First by reversing all the bits of each byte using a galois matrix
multiplication(vgf2p8affineqb, Icelake), and then by reversing the bytes
themselves(pshufb, ssse3).
 2020-10-02 05:56:59 +01:00
ReinUsesLisp
eb00bea1ff backend/x64/exception_handler_posix: Fix signal stack memory leak in SigHandler 
std::malloc was being called inside SigHandler's constructor without a
std::free. This doesn't really matter as SigHandler is used as a
singleton and the OS will reclaim that memory. That said, properly
freeing memory keeps -fsanitize=address quiet.
 2020-10-02 05:56:07 +01:00
Wunkolo
c2d5f6da90 block_of_code: Add HasAVX512_Icelake 
Detect AVX512 feature support up to the [Icelake-level featureset](https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512)
 2020-09-19 15:20:40 +01:00
Lioncash
0e1112b7df Revert "basic_block: Mark move constructor and assignment as noexcept" 
This reverts commit 4f12e86ebb.

Big fan of MSVC preventing standard behavior.
 2020-08-14 16:49:40 -04:00
Lioncash
889635d17d general: Resolve -Wmissing-prototypes warnings 2020-08-14 14:50:09 -04:00
Lioncash
68fea20020 common/assert: Resolve several -Wextra-semi warnings 
Resolves 200+ warnings.
 2020-08-14 14:45:53 -04:00
Lioncash
4f12e86ebb basic_block: Mark move constructor and assignment as noexcept 
Allows the type to play nicely with standard library facilities better
(also we shouldn't be throwing in move operations to begin with).
 2020-08-14 14:38:28 -04:00
Lioncash
34f4d99454 block_of_code: Remove unused variables in GenRunCode() 
These aren't used, so they can be removed.
 2020-08-14 14:35:17 -04:00
Lioncash
29d1758923 ir_matcher: Add missing header guard 2020-08-14 14:32:34 -04:00
MerryMage
6bbc53839f Unsafe Optimization: Extend Unsafe_UnfuseFMA to all FMA-related instructions 2020-07-12 12:45:12 +01:00
MerryMage
d05d95c132 Improve documentation of unsafe optimizations 2020-07-12 12:41:11 +01:00
MerryMage
82417da780 emit_x64{_vector}_floating_point: Add unsafe optimizations for RSqrtEstimate and RecipEstimate 2020-07-11 14:05:57 +01:00
MerryMage
761e95eec0 A64: Add unsafe_optimizations option 
* Strength reduce FMA unsafely
 2020-07-06 21:02:30 +01:00
MerryMage
82868034d3 A32/ASIMD: Ensure decoder table is correct 
* Raise a DecoderError instead of ASSERT-ing on a decode error
* Correct ASIMD decode table
* Write a test which verifies every possible ASIMD instruction
 2020-07-05 18:45:42 +01:00
MerryMage
3c742960a9 simd_three_same: Ensure zero in upper for PairedMinMaxOperation 2020-07-04 11:25:36 +01:00
MerryMage
735738c7b6 A32: Implement ASIMD VPMAX, VPMIN (floating-point) 2020-07-04 11:04:10 +01:00
MerryMage
88e74cb2ba A32: Implement ASIMD VPMAX, VPMIN (integer) 2020-07-04 11:04:10 +01:00
MerryMage
d9914b1d51 simd_permute: Implement VectorUnzip with deinterleave lower 2020-07-04 11:04:10 +01:00
MerryMage
f35aaa017c IR: Add VectorDeinterleave{Even,Odd}Lower 2020-07-04 11:04:10 +01:00
MerryMage
df477c46c2 asimd_load_store_structures: VST1 undef correction 2020-07-04 11:04:10 +01:00
MerryMage
4ba1f8b9e7 Add optimization flags to disable specific optimizations 2020-07-04 11:04:10 +01:00
MerryMage
3eed024caf asimd_three_same: Ignore Q=1 for VPADD (floating-point) 2020-07-04 11:04:10 +01:00
MerryMage
896cb46c89 asimd_*: Standardize order of n and m to reduce confusion 2020-07-04 11:04:10 +01:00
MerryMage
4b8a781c04 emit_x64_floating_point: Introduce ICODE 2020-07-04 11:04:10 +01:00
MerryMage
7022281a0b emit_x64_vector_floating_point: Introduce ICODE 2020-07-04 11:04:10 +01:00
Merry
4f967387c0 asimd_three_regs: Reimplement asimd_VMLAL in terms of WideInstruction 2020-06-27 13:06:46 +01:00
Merry
7997404ee7 A32: Implement ASIMD V{ADD,SUB}{W,L} 2020-06-27 12:58:47 +01:00
Merry
868bd00ab5 A32: Rearrange translators for ASIMD Three Registers 
* Separate Three Registers with Different Lengths from Same Lengths decoders
 2020-06-27 11:15:07 +01:00
Merry
b1ff971a92 backend/x64: Temporarily avoid use of DefineValue(Argument&) 
Issues with inappropriate values in upper bits of values
 2020-06-27 10:52:59 +01:00
MerryMage
8a1f106dba decoder/asimd: Correct names of scalar exceptions 2020-06-25 17:40:11 +01:00
MerryMage
495f58eed8 A32: Implement ASIMD VSHLL 2020-06-24 23:47:13 +01:00
MerryMage
ed48a9d7d5 A32: Implement VFPv5 VRINTX 2020-06-24 22:31:58 +01:00
MerryMage
46445d0866 A64: Remove NaN accuracy setting 
Always do accuracte NaN handling.
 2020-06-24 22:26:10 +01:00
Lioncash
b5df8d1ef8 A32: Implement ASIMD VQDMULL (scalar) 2020-06-23 18:19:42 +01:00
Lioncash
20a2bf29fc A32: Implement ASIMD VQRDMULH (scalar) 2020-06-23 18:19:42 +01:00
Lioncash
ab5efe8632 A32: Implement ASIMD VQDMULH (scalar) 2020-06-23 18:19:42 +01:00
MerryMage
2008fda88b emit_x64_floating_point: Correct error in s16 rounding in EmitFPToFixed 2020-06-22 22:54:38 +01:00
MerryMage
3ea49fc6d6 A32: Implement VFPv3 VCT (between floating-point and fixed-point) 2020-06-22 22:08:58 +01:00
MerryMage
48b2ffdde9 A32: Implement ASIMD VQMOVUN, VQMOVN 2020-06-22 20:02:52 +01:00
MerryMage
52b8039367 A32: Implement VFPv5 VRINT{R,Z} 2020-06-22 19:35:32 +01:00
MerryMage
47bc99ad9f asimd_load_store_structures: Fix 2-byte aligned vld1.16 
Previously incorrectly undefined
 2020-06-22 18:46:22 +01:00
Lioncash
dd8d5497da A32: Implement ASIMD VQRDMULH 2020-06-22 17:31:57 +01:00
Lioncash
0b7a111b54 A32: Implement ASIMD VQDMULH 2020-06-22 17:31:57 +01:00
Lioncash
39488e4aad A32: Implement ASIMD VRSHRN 2020-06-21 23:15:43 +01:00
Lioncash
86b0e5c1c5 A32: Implement ASIMD VQSHRN 2020-06-21 23:15:43 +01:00
Lioncash
85222e3e65 A32: Implement ASIMD VQSHRUN 
We can leverage ShiftRightNarrowing() to implement this.
 2020-06-21 23:15:43 +01:00
MerryMage
562a98bcf9 A32: Implement ASIMD VCVT (between floating-point and fixed-point) 2020-06-21 20:23:40 +01:00
MerryMage
6f56043a73 A32: Implement ASIMD VFMA, VFMS 2020-06-21 20:21:53 +01:00
Lioncash
aa0358d324 A32: Implement ASIMD VMLAL/VMLSL (integer) 2020-06-21 20:03:19 +01:00
Lioncash
eab26b404a A32: Implement ASIMD VABAL 2020-06-21 20:01:08 +01:00
Lioncash
98581839ca A32: Implement ASIMD VABDL 2020-06-21 19:55:00 +01:00
MerryMage
db85e7ced5 asimd: Add missing three registers of different lengths instructions 2020-06-21 19:54:32 +01:00
Lioncash
95919594d1 A32: Implement ASIMD VQSHL/VQSHLU (immediate) 2020-06-21 19:26:30 +01:00
MerryMage
3557576ece A32: Implement ASIMD AESD, AESE, AESIMC, AESMC 2020-06-21 18:39:57 +01:00
Fernando Sahmkow
2fa1c1d13c A32: Allow cleaning up exclusive state from the interface. 
This function is normally required for emulating certain OS mechanisms.
 2020-06-21 18:18:33 +01:00
MerryMage
df58a429ee A32: Implement ASIMD VQRSHRN 2020-06-21 17:41:18 +01:00
MerryMage
589d717af5 A32: Implement ASIMD VQRSHRUN 2020-06-21 17:41:18 +01:00
MerryMage
e009d99924 A32: Implement ASIMD VSHRN 2020-06-21 17:41:18 +01:00