dynarmic

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3cb98e1560 fp: Move fp_util to fp/util MerryMage 2018-06-26 20:54:42 +0100
c41a38b13e fp: Add FPSR MerryMage 2018-06-26 20:51:25 +0100
66381352f3 fp: Add FPInfo MerryMage 2018-07-14 09:41:36 +0100
d21659152c safe_ops: Implement safe shifting operations MerryMage 2018-06-28 21:45:13 +0100
b00fe23b91 bit_util: Implement MostSignificantBit MerryMage 2018-06-28 21:44:35 +0100
95ad0d0a66 bit_util: Use Ones to implement Bits MerryMage 2018-06-27 14:37:52 +0100
62b640b2fa bit_util: Add ClearBit and ModifyBit MerryMage 2018-06-26 20:50:39 +0100
8651c2d10e u128: Implement u128 MerryMage 2018-06-28 21:44:21 +0100
e7409fdfe4 A64: Implement UCVTF (vector, integer)'s double/single-precision variant Lioncash 2018-07-12 09:57:08 -0400
4aa4885ba7 ir: Add opcodes for vector conversion of u32/u64 to floating-point Lioncash 2018-07-12 09:02:27 -0400
fcae4e2418 simd_three_different: Deduplicate common implementations Lioncash 2018-07-14 16:13:37 -0400
9c0d5cf15c floating_point_conversion_integer: Handle S64/U64 -> F32 conversions in SCVTF_float_int and UCVTF_float_int Lioncash 2018-07-09 19:50:09 -0400
7a84b6e8d8 ir: Add opcodes for converting S64 and U64 to single-precision floating-point values Lioncash 2018-07-09 19:32:30 -0400
066061fa50 constant_pool: Remove unnecessary std::memset from constructor Lioncash 2018-07-15 02:36:19 -0400
9c4f234417 fuzz_with_unicorn: Avoid self-modifying code MerryMage 2018-07-15 11:58:53 +0100
9f8c6f60f5 fuzz_with_unicorn: Configure as per qemu max configuration MerryMage 2018-07-14 08:49:27 +0100
64d4e40081 tests/A32/testenv: Add type aliases for register arrays Lioncash 2018-07-13 14:19:22 -0400
a25bacc436 tests/unicorn: Add type aliases to the Unicorn class Lioncash 2018-07-13 13:41:19 -0400
a1d6a86e8c A64: Implement ADDV Lioncash 2018-07-13 21:01:57 -0400
35026a6ce3 emit_x64_vector: Vectorize fallback path for EmitVectorMaxU32() Lioncash 2018-07-13 20:20:17 -0400
245c903129 simd_three_same: Join FPAbsoluteComparison() into FPCompareRegister() Lioncash 2018-07-13 18:58:39 -0400
9912836b59 A64: Implement scalar double/single-precision variants of FACGE, FACGT, FCMEQ, FCMGE, FCMGT Lioncash 2018-07-13 18:37:10 -0400
0b97e9bd8d emit_x64_floating_point: Fix EmitFPU64ToDouble for TowardsMinusInfinity rounding mode MerryMage 2018-07-14 07:08:44 +0100
a2eb9a02e0 backend_x86: Add FPSCR_RMode to EmitContext MerryMage 2018-07-14 07:08:15 +0100
8c65d58cb8 tests/A64: Randomize FPCR.RMode for single random instruction MerryMage 2018-07-14 07:07:40 +0100
d875c08ebf fp: Extract common RoundingMode enum MerryMage 2018-06-26 15:10:44 +0100
7d52d7bef8 inst_gen: Compress loop into std::any_of in IsInvalidInstruction() Lioncash 2018-07-13 09:49:53 -0400
d909b0919e fuzz_with_unicorn: Move std::vector outside loop in small random block test case Lioncash 2018-07-13 09:39:56 -0400
ef57d75b32 fuzz_with_unicorn: Temporarily disable FDIV MerryMage 2018-07-12 22:31:31 +0100
ec0a91d6ee tests/A64: Test small blocks MerryMage 2018-01-26 18:50:57 +0000
330e6111fa fuzz_with_unicorn: Randomize FPCR.RMode MerryMage 2018-07-12 13:52:29 +0100
3714bc0ed4 floating_point_conversion_integer: Use FPS64ToDouble and FPU64ToDouble in SCVTF_float_int and UCVTF_float_int Lioncash 2018-07-09 19:15:54 -0400
b97358075e simd_scalar_two_register_misc: Handle 64-bit case in SCVTF and UCVTF's scalar double/single-precision variant Lioncash 2018-07-09 17:25:13 -0400
7252293184 emit_x64_floating_point: Correct use of UseGpr() in EmitFPU32ToDouble() and EmitFPU32ToSingle() Lioncash 2018-07-09 18:32:36 -0400
fbd7623fe5 emit_x64_floating_point: Add AVX512F conversion operations to EmitFPU32ToSingle() and EmitFPU32ToDouble() Lioncash 2018-07-09 17:46:31 -0400
3a41465eaf ir: Add opcodes for converting S64 and U64 to double-precision values Lioncash 2018-07-09 17:14:00 -0400
436ca80bcd Merge branch 'global_monitor' MerryMage 2018-07-07 22:52:50 +0100
0f4bf26e05 simd_two_register_misc: Utilize FPVectorAbs in FABS implementations Lioncash 2018-07-07 14:54:44 -0400
821cff1227 A64: Add ClearExclusiveState method MerryMage 2018-07-04 00:03:36 +0100
81e572c78c ir: Extend FPVectorAbs opcode to also handle 16-bit elements for FP16 Lioncash 2018-07-07 14:48:16 -0400
2a8de5f733 a64_emit_x64: Clear exclusive state in EmitA64CallSupervisor MerryMage 2018-06-05 13:05:41 +0100
53dbb6a92a A64: Implement FACGE's vector single/double precision variants Lioncash 2018-07-06 22:49:34 -0400
57f7c7e1b0 Implement global exclusive monitor MerryMage 2018-06-05 12:27:37 +0100
6912a02d9b A64: Implement FACGT's vector single/double precision variants Lioncash 2018-07-06 22:35:33 -0400
85234338d3 a64_emit_x64: Simplify EmitExclusiveWrite MerryMage 2018-06-05 12:26:05 +0100
fc731dddae ir: Add opcodes for performing vector absolute floating-point values Lioncash 2018-07-06 21:55:42 -0400
2fc6b33829 CMakeLists: Add missing files MerryMage 2018-06-05 12:25:16 +0100
0bee648b4f emit_x64_vector: Deduplicate a bit of code in EmitVectorSetElement{8, 32, 64} functions Lioncash 2018-07-06 20:08:20 -0400
593eca7fb1 A64: Implement load/store single structure instructions Lioncash 2018-07-04 14:05:53 -0400
b6e223fc58 emit_x64_vector: Deduplicate a bit of code within EmitVectorGetElement8() Lioncash 2018-07-06 16:55:01 -0400
eb3ca7f65b tests: Add print_info program MerryMage 2018-06-27 15:07:28 +0100
be354dbfd0 ir/basic_block: Add missing U16 immediate type to DumpBlock MerryMage 2018-06-27 15:06:20 +0100
5503ff28c3 llvm_disassemble: Allow disassembly of invalid AArch64 instructions MerryMage 2018-06-27 15:06:04 +0100
47a4d93403 externals: Update catch to v2.2.3 Lioncash 2018-06-09 17:07:55 -0400
9e75d08860 A64: Implement FABD's scalar single/double precision variant Lioncash 2018-06-08 20:44:52 -0400
d898d1779d A64: Implement FABD's vector single/double precision variant Lioncash 2018-06-08 20:06:46 -0400
8a4f8aed06 ir: Add opcode for performing FP vector absolute differences Lioncash 2018-06-08 19:49:42 -0400
ba84e7a8de A64: Implement FNMSUB MerryMage 2018-04-04 19:02:45 +0100
a1042cfcd8 A64: Implement FNMADD MerryMage 2018-04-04 19:01:50 +0100
0d83032a6f A64: Implement FMSUB MerryMage 2018-04-04 19:00:28 +0100
69e00d225c A64: Implement FMADD MerryMage 2018-06-06 19:57:58 +0100
8c90fcf58e IR: Implement FPMulAdd MerryMage 2018-06-06 20:03:12 +0100
24e3299276 A64: Implement FCMGT, FCMGE (register) vector double and single precision variants Lioncash 2018-06-03 20:28:16 -0400
350bc70be8 A64: Implement FCMGT, FCMGE, FCMLE, FCMLT (zero) vector double and single precision variants. Lioncash 2018-06-03 19:46:54 -0400
c695da1cf3 ir: Add opcode for floating-point GE and GT comparisons Lioncash 2018-06-03 19:39:21 -0400
d86fea0d28 A64: Implement FCMEQ (zero)'s vector single and double precision variant Lioncash 2018-06-02 16:39:57 -0400
9bec354791 A64: Implement FCMEQ (register)'s vector single and double precision variant Lioncash 2018-06-02 16:17:15 -0400
5ce187a54e ir: Add opcodes for floating-point vector equalities Lioncash 2018-06-02 16:11:40 -0400
e64978ed89 fuzz_with_unicorn: Make float_numbers in floating-point tests constexpr Lioncash 2018-05-26 17:45:01 -0400
cf188448d4 emit_x64_vector: Vectorize fallback case in EmitVectorMultiply64() Lioncash 2018-05-23 16:28:29 -0400
954deff2d4 emit_x64_vector: Add break to final case in EmitVectorRoundingHalvingAddUnsigned() Lioncash 2018-05-26 16:19:52 -0400
11a92eaaef A64: Implement SRHADD and URHADD Lioncash 2018-05-23 17:35:30 -0400
bc718c5b28 ir: Add opcodes for performing rounding halving adds Lioncash 2018-05-23 16:52:31 -0400
054549da35 emit_x64_vector: Simplify AVX-512 codepath in EmitVectorMultiply64 Lioncash 2018-05-14 23:02:38 -0400
cb456f914b A64: Implement UMLAL{2}, UMLSL{2}, and UMULL{2} Lioncash 2018-05-15 10:58:04 -0400
3576c02d91 A64: Implement SMLSL{2} Lioncash 2018-05-15 10:50:28 -0400
ada5c0b2fa A64: Implement SMLAL{2} Lioncash 2018-05-15 10:42:13 -0400
2d1aca25e6 A64: Implement SMULL{2} Lioncash 2018-05-15 10:20:03 -0400
329137a277 fuzz_with_unicorn: Remove exclusion of FMOV (imm) for FP-16 floats Lioncash 2018-05-15 22:35:33 -0400
c5ae9107a9 A64: Implement SABAL/SABAL2 and SABDL/SABDL2 Lioncash 2018-05-12 15:30:05 -0400
26d4473851 A64: Implement UABAL/UABAL2 Lioncash 2018-05-12 14:56:24 -0400
3397742c74 A64: Implement UABDL/UABDL2 Lioncash 2018-05-12 14:42:48 -0400
6de5ed96e5 emit_x64_vector: Emit VPMULLQ in EmitVectorMultiply64 on AVX-512{DQ, VL} capable CPUs Lioncash 2018-05-14 12:11:50 -0400
9054d1c20b A64: Implement LDR (literal, SIMD&FP) Lioncash 2018-05-14 09:12:56 -0400
0da5e949a8 Correct typo in DataCacheOperation enum Lioncash 2018-05-14 09:44:18 -0400
9736e2cce2 A64: Implement FABS' half-precision variant Lioncash 2018-05-11 11:09:25 -0400
6e5750e4ec A64: Implement FABS' single and double precision variant Lioncash 2018-05-11 10:55:41 -0400
7bce8d8757 A64: Implement URSHR (scalar) and URSRA (scalar) Lioncash 2018-05-11 10:42:31 -0400
1e70a589b0 A64: Implement SRSRA (scalar) Lioncash 2018-05-11 10:31:30 -0400
998aef07f6 A64: Implement SRSHR (scalar) Lioncash 2018-05-11 09:34:49 -0400
7c0250e9f8 A64: Implement SABA Lioncash 2018-05-08 16:42:59 -0400
f00789e6f7 A64: Implement SABD Lioncash 2018-05-08 16:33:28 -0400
1e10017f4b ir: Add opcodes for signed absolute differences Lioncash 2018-05-08 15:39:37 -0400
d3b44c1b5a decoder_detail: use structured bindings Tillmann Karras 2018-05-12 07:17:18 +0100
ed11c7d904 CMakeLists: Add detection for Aarch64 compiler environments Lioncash 2018-05-09 14:18:23 -0400
f745eb28bf simd_two_register_misc: Handle 64-bit case for SCVTF_int_4 Lioncash 2018-05-08 11:53:59 -0400
3f6c529da2 ir: Add opcode to perform the vector conversion S64->F64 Lioncash 2018-05-08 11:18:13 -0400
0e61ee6bf6 A64: Implement SHLL/SHLL2 Lioncash 2018-05-08 10:14:06 -0400
43e6e98c3b A64: Add missing decoding for PRFM (unscaled offset) Lioncash 2018-05-08 08:14:08 -0400
f2a85d5601 A64: Implement UHSUB Lioncash 2018-05-07 12:50:47 -0400