mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
1050 commits 1 branch 0 tags 34 MiB
Commit graph

896 commits

Author SHA1 Message Date
Lioncash
00af6eeab9 A64: Implement SADDW/SADDW2 2020-04-22 20:46:15 +01:00
MerryMage
78a047f0f9 A64: Implement EXT 2020-04-22 20:46:15 +01:00
MerryMage
3472f371df IR: Implement VectorExtract, VectorExtractLower IR instructions 2020-04-22 20:46:15 +01:00
MerryMage
8bba37089e A64: Implement UADDW 2020-04-22 20:46:15 +01:00
MerryMage
5c47f03888 A64: Implement FMUL (vector) 2020-04-22 20:46:15 +01:00
Lioncash
a6e264c2dd A64: Implement UABA 
Now that we have unsigned absolute difference capabilities, we can just use this to
append onto the result via a vector add.
 2020-04-22 20:46:15 +01:00
Lioncash
c2e7364d3e A64: Implement UABD 2020-04-22 20:46:15 +01:00
Lioncash
ad5cf584ce ir: Add opcodes for performing vector unsigned absolute differences 2020-04-22 20:46:15 +01:00
Lioncash
7780af56e3 ir_emitter: Make immediate member functions const qualified 
These don't modify class state
 2020-04-22 20:46:15 +01:00
Lioncash
701f43d61e IR: Add opcodes for interleaving upper-order bytes/halfwords/words/doublewords 
I should have added this when I introduced the functions for interleaving
low-order equivalents for consistency in the interface.
 2020-04-22 20:46:15 +01:00
Lioncash
94f0fba16b A64: Implement SHA1H 
This is a fairly trivial instruction it's essentially:

result = ROL(data, 30);
 2020-04-22 20:46:15 +01:00
Lioncash
3985f7bf84 emit_x64_data_processing: Deduplicate some code in zero-extension functions 
EmitZeroExtendByteToLong() can be implemented in terms of EmitZeroExtendByteToWord() and
EmitZeroExtendHalfToLong() can be implemented in terms of EmitZeroExtendHalfToWord().
 2020-04-22 20:46:15 +01:00
Lioncash
40ec25356b A64: NOP immediate variant of PRFM 
Makes behavior identical to the literal variant of PRFM. Given this is simply a hint instruction,
this is valid behavior. The upside is that we don't fall back to Unicorn unnecessarily whenever
the instruction is encountered.
 2020-04-22 20:46:15 +01:00
MerryMage
e7b60189b3 abi: Missing includes' 2020-04-22 20:46:15 +01:00
MerryMage
cdc5c3ad95 emit_x64_floating_point: Near jump instead of short jump in FPMinNumberic{32,64} 2020-04-22 20:46:15 +01:00
Lioncash
73b9e4b276 A64: system: Use an enum class for MRS/MSR register encodings 
Reduces the need to manually write out the register bit encodings repeatedly.
 2020-04-22 20:46:15 +01:00
MerryMage
df4ee0f51e emit_X64_floating_point: Near jmp to end instead of short jmp 
Jump destination can be further than what can be reached in a short
jump under some FPCR options.
 2020-04-22 20:46:15 +01:00
Lioncash
b8d5765f9b emit_x64_vector: Fix typo in VectorShuffleImpl 
This is supposed to be pshufd, not pshufw (which only allows a 64-bit operand)
 2020-04-22 20:46:15 +01:00
Lioncash
586b00d11d A64: Implement REV64 2020-04-22 20:46:15 +01:00
Lioncash
ade595e377 bit_util: Do nothing in RotateRight if the rotation amount is zero 
Without this sanitizing it's possible to perform a shift with a shift
amount that's the same size as the type being shifted. This actually
occurs when decoding ORR variants.

We could get fancier here and make this branchless, but we don't
really use RotateRight in any performance intensive areas.
 2020-04-22 20:46:15 +01:00
Lioncash
9128988dc3 A64: Implement REV32 (vector) 2020-04-22 20:46:15 +01:00
Lioncash
6b0010c940 ir: Add IR opcodes for emitting vector shuffles 
This uses the ARM terminology for sizes (Halfword -> 2 bytes, Word -> 4 bytes)
as opposed to the x86 terminology of (Word -> 2 bytes, Double word -> 4 bytes)
 2020-04-22 20:46:15 +01:00
Lioncash
eb2d28d2b1 emit_x64_vector_floating_point: Fix out of bounds array access in EmitVectorOperation64 2020-04-22 20:46:15 +01:00
Lioncash
6ad1bce5e0 A64: Implement REV16 (vector) 2020-04-22 20:46:15 +01:00
Lioncash
6177c2c63d CMakeLists: Add fp_util, macro_util and math_util headers 
Allows the headers to show up within IDEs
 2020-04-22 20:46:15 +01:00
Lioncash
7a66224d9a A64: Implement EOR3 and BCAX 2020-04-22 20:46:15 +01:00
MerryMage
be5047c7c2 impl: Update PC when raising exception 2020-04-22 20:46:15 +01:00
MerryMage
49cc6d7fad A64: Implement FDIV (vector) 2020-04-22 20:46:15 +01:00
MerryMage
fd075d8d68 system: Raise exception for YIELD, WFE, WFI, SEV, SEVL 2020-04-22 20:46:15 +01:00
MerryMage
c832cec96d Correct FPSR and FPCR 2020-04-22 20:46:15 +01:00
MerryMage
147284427b A64: Implement USHL 2020-04-22 20:46:15 +01:00
MerryMage
fd8f4c1195 A64: Implement UCVTF (vector, integer), scalar variant 2020-04-22 20:46:15 +01:00
MerryMage
be57608353 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) 2020-04-22 20:46:15 +01:00
MerryMage
e4697b1676 A64: Implement system register TPIDR_EL0 2020-04-22 20:46:15 +01:00
MerryMage
e3da92024e A64: Implement system registers FPCR and FPSR 2020-04-22 20:46:15 +01:00
MerryMage
9e4e4e9c1d A64: Implement system register CNTPCT_EL0 2020-04-22 20:46:15 +01:00
MerryMage
1e15283d00 A64: Implement system register CTR_EL0 2020-04-22 20:46:15 +01:00
MerryMage
58fbb3ff1b A64: Implement NEG (vector) 2020-04-22 20:46:15 +01:00
MerryMage
710d09471b IR: Add IR instruction ZeroVector 2020-04-22 20:46:15 +01:00
MerryMage
2721bb5ace emit_x64_floating_point: Add maybe_unused to preprocess parameter 2020-04-22 20:46:15 +01:00
MerryMage
0575e7421b A64: Implement FMINNM (scalar) 2020-04-22 20:46:15 +01:00
MerryMage
1c9804ea07 A64: Implement FMAXNM (scalar) 2020-04-22 20:46:15 +01:00
MerryMage
1dfce0894d constant_pool: Add frame parameter 2020-04-22 20:46:14 +01:00
MerryMage
bd2b415850 A64: Implement ADDP (scalar) 2020-04-22 20:46:14 +01:00
MerryMage
84f1c9b7f4 reg_alloc: Only exchange GPRs 2020-04-22 20:46:14 +01:00
MerryMage
9df3793af0 A64: Implement DUP (element), scalar variant 2020-04-22 20:46:14 +01:00
MerryMage
6541ec064d emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0 2020-04-22 20:46:14 +01:00
MerryMage
2080a51f41 A64: Implement FMAX (scalar), FMIN (scalar) 2020-04-22 20:46:14 +01:00
MerryMage
7c193485e1 a64/config: Allow NaN emulation accuracy to be set 2020-04-22 20:46:14 +01:00
MerryMage
a3df46a75a a64_emit_x64: Add conf to A64EmitContext 2020-04-22 20:46:14 +01:00
MerryMage
0e157b0198 A64: Implement FSQRT (scalar) 2020-04-22 20:46:14 +01:00
MerryMage
07520f32c3 backend_x64: Accurately handle NaNs 2020-04-22 20:46:14 +01:00
MerryMage
e97581d063 fuzz_with_unicorn: Print AArch64 disassembly 2020-04-22 20:46:14 +01:00
MerryMage
01c1e9017e T32: Add initial decoder list 2020-04-22 20:46:14 +01:00
MerryMage
ccf7df057b simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector) 2020-04-22 20:46:14 +01:00
MerryMage
8cebb87d0d A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero) 2020-04-22 20:46:14 +01:00
MerryMage
7f68d556ab decoder/a64: Rearrange SIMD two-register misc decoders 2020-04-22 20:46:14 +01:00
MerryMage
d5af052f06 A64: Implement CMGE (register) 2020-04-22 20:46:14 +01:00
MerryMage
9d85991906 A64: Implement CMHI, CMHS 2020-04-22 20:46:14 +01:00
MerryMage
e2b9b7c5b0 IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned} 2020-04-22 20:46:14 +01:00
MerryMage
0df6725f73 A64: Implement SMAX, SMIN, UMAX, UMIN 2020-04-22 20:46:14 +01:00
MerryMage
47c0ad0fc8 IR: Implement Vector{Max,Min}{Signed,Unsigned} 2020-04-22 20:46:14 +01:00
MerryMage
adb7f5f86f A64: Implement CMGT (register) 2020-04-22 20:46:14 +01:00
MerryMage
f4775910f5 IR: Implement VectorGreaterSigned 2020-04-22 20:46:14 +01:00
MerryMage
1f5b3bca43 Exclusive fixups 
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
 2020-04-22 20:46:14 +01:00
MerryMage
f3fa4a042f a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning) 2020-04-22 20:46:14 +01:00
MerryMage
8698f057d0 A64: Implement STXP, STLXP, LDXP, LDAXP 2020-04-22 20:46:14 +01:00
MerryMage
2a6619d59c A64: Implement CLREX 2020-04-22 20:46:14 +01:00
MerryMage
b7a2c1a7df A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR 2020-04-22 20:46:14 +01:00
MerryMage
a6cc667509 Direct Page Table Access: Handle address spaces less than the full 64-bit in size 2020-04-22 20:46:14 +01:00
MerryMage
f45a5e17c6 Implement direct page table access 2020-04-22 20:46:14 +01:00
MerryMage
bfd3e30c75 callbacks: Member functions should be const 2020-04-22 20:46:14 +01:00
MerryMage
9f2f08db8d a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call 2020-04-22 20:46:14 +01:00
MerryMage
6c4773e85b abi: Add RAX to ABI_ALL_CALLER_SAVE 2020-04-22 20:46:14 +01:00
MerryMage
8756487554 A64: Partially implement MRS 2020-04-22 20:46:14 +01:00
MerryMage
bfd65bedfe A64: Implement DSB, DMB 2020-04-22 20:46:14 +01:00
MerryMage
5edd623b9d Implement DC instructions 2020-04-22 20:46:14 +01:00
Lioncash
a9153218bd A64: Implement NOT (vector) 2020-04-22 20:46:14 +01:00
MerryMage
2cb0a699ba IR: Implement FPMax, FPMin 2020-04-22 20:46:14 +01:00
MerryMage
aed4fd3ec3 A64: Implement FADD (vector), vector variant 2020-04-22 20:46:14 +01:00
MerryMage
98c8e7d1af IR: Implement FPVectorAdd 2020-04-22 20:46:14 +01:00
MerryMage
5f77ab28ee A64: Implement SSHLL, SSHLL2 2020-04-22 20:46:14 +01:00
MerryMage
eae518a338 IR: Implement VectorSignExtend 2020-04-22 20:46:14 +01:00
MerryMage
3738043e58 A64: Implement DUP (element), vector variant 2020-04-22 20:46:14 +01:00
MerryMage
ce7628b6b5 load_store_multiple_structures: Improve IR codegen for selem == 1 case 2020-04-22 20:46:14 +01:00
MerryMage
f1cb5581c9 A64: Implement FSUB (vector) 2020-04-22 20:46:14 +01:00
MerryMage
b9cd345ddc IR: Implement FPVectorSub 2020-04-22 20:46:14 +01:00
MerryMage
851fc83445 emit_x64_vector: EmitOneArgumentFallback 2020-04-22 20:46:14 +01:00
MerryMage
f378d2ef1b Forward declare IR::Opcode and IR::Type where possible 2020-04-22 20:46:14 +01:00
MerryMage
6c9b4f0114 A64: Implement CNT 2020-04-22 20:46:14 +01:00
MerryMage
303088a51e IR: Implement VectorPopulationCount 2020-04-22 20:46:14 +01:00
MerryMage
1dd2b33b87 A64: Implement MLS (vector) 2020-04-22 20:46:14 +01:00
MerryMage
5eac3abf52 A64: Implement MLA (vector) 2020-04-22 20:46:14 +01:00
MerryMage
bf2cd92da9 emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64 2020-04-22 20:46:14 +01:00
MerryMage
b062266b8e emit_x64_vector: More explicit lambda decay 2020-04-22 20:46:14 +01:00
MerryMage
3afd2fcbad A64: Implement MUL (vector) 2020-04-22 20:46:14 +01:00
MerryMage
b6de612e01 IR: Implement VectorMultiply 2020-04-22 20:46:14 +01:00
MerryMage
90a053a5e4 emit_x64_vector: Order alphabetically 2020-04-22 20:46:14 +01:00
MerryMage
e7041d7196 A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP) 2020-04-22 20:46:14 +01:00
MerryMage
a455ff70c9 decoder/a64: Don't rearrange unrelated decoders 2020-04-22 20:46:14 +01:00