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290 commits

Author SHA1 Message Date
Lioncash
d1f5b084b4 A64: Handle S32->F32 case for SCVTF (vector) 2020-04-22 20:46:17 +01:00
Lioncash
b8587d8e34 A64: Implement SHA512SU1 2020-04-22 20:46:16 +01:00
Lioncash
44d846045a A64: Implement SHA512SU0 2020-04-22 20:46:16 +01:00
Lioncash
ca903c1585 A64: Implement SHA256H and SHA256H2 2020-04-22 20:46:16 +01:00
MerryMage
e4237c44eb A64: Implement SCVTF (vector, integer), scalar varaint 2020-04-22 20:46:16 +01:00
MerryMage
bfba38d0b6 impl: Reorganize scalar two-register misc instructions 2020-04-22 20:46:16 +01:00
Lioncash
ea582b17cc A64: Implement SHA256SU1 2020-04-22 20:46:16 +01:00
Lioncash
06c5dcaf5e simd_two_register_misc: Add missing zeroing of the vector for CMGT and CMLT 2020-04-22 20:46:16 +01:00
Lioncash
0d50d7314b A64: Implement CMGE (zero)'s vector variant 2020-04-22 20:46:16 +01:00
Lioncash
ab35dc0e78 A64: Implement MLS (by element) 2020-04-22 20:46:16 +01:00
Lioncash
1651e60462 A64: Implement MUL (by element) 2020-04-22 20:46:16 +01:00
MerryMage
a86d4093cd A64: Implement MLA (by element) 2020-04-22 20:46:16 +01:00
Lioncash
7f47402609 A64: Implement ABS (scalar) 2020-04-22 20:46:16 +01:00
Lioncash
c8eb4528be A64: Implement SHA256SU0 2020-04-22 20:46:16 +01:00
Lioncash
181c3b0790 A64: Implement SHA1M 2020-04-22 20:46:16 +01:00
Lioncash
47bc97a71b A64: Implement SHA1P 2020-04-22 20:46:16 +01:00
Lioncash
718f3e9bb4 A64: Implement scalar variants of CMEQ, CMGT, and CMGE zero comparison instructions 
These can trivially use the ScalarCompare helper function.
 2020-04-22 20:46:16 +01:00
Lioncash
3ad4e547e4 A64: Implement scalar variant of NEG 2020-04-22 20:46:16 +01:00
Lioncash
b4f3051e4b simd: Relocate REV16, REV32 and REV64 vector variants to the proper file 
These aren't scalar instruction variants.
 2020-04-22 20:46:16 +01:00
Lioncash
19e276d10f A64: Implement CMEQ (register, scalar) 2020-04-22 20:46:16 +01:00
Lioncash
5b8c9e5146 A64: Implement CMHS (register, scalar) 2020-04-22 20:46:16 +01:00
Lioncash
78bb12276a A64: Implement CMHI (register, scalar) 2020-04-22 20:46:16 +01:00
Lioncash
c18b20b8d1 A64: Implement CMGE (register, scalar) 2020-04-22 20:46:16 +01:00
Lioncash
755981d0da A64: Implement CMGT (register, scalar) 2020-04-22 20:46:16 +01:00
Lioncash
da6627124b A64: Implement SHA1C 2020-04-22 20:46:16 +01:00
Lioncash
3c013bd9f8 A64: Implement SLI (scalar) 2020-04-22 20:46:16 +01:00
Lioncash
154cac594a A64: Implement SRI (scalar) 2020-04-22 20:46:16 +01:00
Lioncash
205ca6b4cb A64: Implement SHA1SU1 2020-04-22 20:46:16 +01:00
Lioncash
16a001b9ff A64: Implement SHA1SU0 2020-04-22 20:46:16 +01:00
Lioncash
3b6db59850 A64: Implement TRN2 2020-04-22 20:46:16 +01:00
Lioncash
30e158f8d0 A64: Implement TRN1 2020-04-22 20:46:16 +01:00
Lioncash
52cad2d9d0 A64: Implement SSRA (scalar) 2020-04-22 20:46:16 +01:00
Lioncash
255a33936d A64: Implement SSHR (scalar) 2020-04-22 20:46:16 +01:00
Lioncash
6723b00497 A64: Implement USRA (scalar) 2020-04-22 20:46:16 +01:00
Lioncash
d56fa8f735 A64: Implement USHR (scalar) 2020-04-22 20:46:16 +01:00
Lioncash
870e418b0b A64: Implement SHL (scalar) 2020-04-22 20:46:16 +01:00
Lioncash
97f2bea4f2 A64: Implement SM3PARTW1 2020-04-22 20:46:16 +01:00
Lioncash
e268b110f0 simd_sha512: Simplify RAX1 
Now that the vector rotation helpers are in, replace the explicit
shifting with the relevant helper function that does the same thing.

Simply tidies up code; no behavioral changes are made.
 2020-04-22 20:46:16 +01:00
Lioncash
20d2491267 A64: Implement SM3PARTW2 2020-04-22 20:46:16 +01:00
Lioncash
8a60a63a8b A64: Implement SM3TT2B 2020-04-22 20:46:16 +01:00
Lioncash
b3d4c02098 A64: Implement SM3TT2A 2020-04-22 20:46:16 +01:00
Lioncash
7fbccabd81 A64: Implement SM3TT1B 2020-04-22 20:46:16 +01:00
Lioncash
769373b3ed A64: Implement SM3TT1A 2020-04-22 20:46:16 +01:00
Lioncash
2d269fdcc7 simd_shift_by_immediate: Merge signed/unsigned helper functions 
Gets rid of a little more code duplication.
 2020-04-22 20:46:16 +01:00
Lioncash
d5461be6b4 A64: Implement SM3SS1 2020-04-22 20:46:16 +01:00
Lioncash
2db032ac83 A64: Implement SRI (vector) 2020-04-22 20:46:16 +01:00
Lioncash
11005cfe26 A64: Implement SLI (vector) 2020-04-22 20:46:16 +01:00
Lioncash
e3d9bf55e7 A64: Implement SRSRA (vector) 2020-04-22 20:46:16 +01:00
Lioncash
bc6016cad7 A64: Implement SRSHR (vector) 2020-04-22 20:46:16 +01:00
MerryMage
6c9c829a08 imm: Add additional bit position checks to Imm::Bits 2020-04-22 20:46:16 +01:00
Lioncash
a2f8cdf0a3 A64: Implement SSUBL/SSUBL2 2020-04-22 20:46:16 +01:00
Lioncash
d456fb85c8 A64: Implement SADDL/SADDL2 2020-04-22 20:46:16 +01:00
Lioncash
5c9e7f328d A64: Implement USUBL/USUBL2 2020-04-22 20:46:16 +01:00
Lioncash
88d70e3b8a A64: Implement UADDL/UADDL2 2020-04-22 20:46:16 +01:00
Lioncash
4b3d70de5f simd_shift_by_immediate: Factor out common code in shift instructions 
Gets rid of partial duplication of the same code for instructions that only have a small behavior difference to them.

e.g. The only difference between SSHR and SSRA is that SSRA adds an accumulator before storing the result.
 2020-04-22 20:46:16 +01:00
Lioncash
56803f5203 A64: Implement URSRA (vector) 2020-04-22 20:46:16 +01:00
Lioncash
8afdf4b23d A64: Implement URSHR (vector) 2020-04-22 20:46:16 +01:00
Lioncash
16613ee066 A64: Implement RSHRN/RSHRN2 2020-04-22 20:46:15 +01:00
Lioncash
937990fd2a A64: Implement SHRN/SHRN2 2020-04-22 20:46:15 +01:00
Lioncash
80e005e5b5 A64/translate: Amend I() to also handle u8 and u16 immediates 
This is necessary for instructions like SRSHR, and other related instructions.
 2020-04-22 20:46:15 +01:00
MerryMage
7969871aa3 A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated 2020-04-22 20:46:15 +01:00
MerryMage
5c95e28ed0 A64: Implement ZIP2 2020-04-22 20:46:15 +01:00
MerryMage
871aefb9a0 decoder/a64: Tweak ordering algorithm 
Ensuring only instruction families are sorted with each other in
the fashion previously devised does not admit a total ordering.
 2020-04-22 20:46:15 +01:00
Lioncash
83ff7a43d1 A64: Implement RBIT (vector) 2020-04-22 20:46:15 +01:00
Lioncash
9de60b60bb A64/translate: Amend instruction prototypes erroneously marked as taking Reg 
Makes the prototypes consistent
 2020-04-22 20:46:15 +01:00
Lioncash
cf81f04ed3 A64: Implement RAX1 2020-04-22 20:46:15 +01:00
Lioncash
7bcb1c115a A64: Implement ABS (vector) 2020-04-22 20:46:15 +01:00
Lioncash
84d49309b9 A64: Implement USUBW/USUBW2 2020-04-22 20:46:15 +01:00
Lioncash
e20fce6b5a A64: Implement SSUBW/SSUBW2 2020-04-22 20:46:15 +01:00
Lioncash
00af6eeab9 A64: Implement SADDW/SADDW2 2020-04-22 20:46:15 +01:00
MerryMage
78a047f0f9 A64: Implement EXT 2020-04-22 20:46:15 +01:00
MerryMage
8bba37089e A64: Implement UADDW 2020-04-22 20:46:15 +01:00
MerryMage
5c47f03888 A64: Implement FMUL (vector) 2020-04-22 20:46:15 +01:00
Lioncash
a6e264c2dd A64: Implement UABA 
Now that we have unsigned absolute difference capabilities, we can just use this to
append onto the result via a vector add.
 2020-04-22 20:46:15 +01:00
Lioncash
c2e7364d3e A64: Implement UABD 2020-04-22 20:46:15 +01:00
Lioncash
94f0fba16b A64: Implement SHA1H 
This is a fairly trivial instruction it's essentially:

result = ROL(data, 30);
 2020-04-22 20:46:15 +01:00
Lioncash
40ec25356b A64: NOP immediate variant of PRFM 
Makes behavior identical to the literal variant of PRFM. Given this is simply a hint instruction,
this is valid behavior. The upside is that we don't fall back to Unicorn unnecessarily whenever
the instruction is encountered.
 2020-04-22 20:46:15 +01:00
Lioncash
73b9e4b276 A64: system: Use an enum class for MRS/MSR register encodings 
Reduces the need to manually write out the register bit encodings repeatedly.
 2020-04-22 20:46:15 +01:00
Lioncash
586b00d11d A64: Implement REV64 2020-04-22 20:46:15 +01:00
Lioncash
9128988dc3 A64: Implement REV32 (vector) 2020-04-22 20:46:15 +01:00
Lioncash
6ad1bce5e0 A64: Implement REV16 (vector) 2020-04-22 20:46:15 +01:00
Lioncash
7a66224d9a A64: Implement EOR3 and BCAX 2020-04-22 20:46:15 +01:00
MerryMage
be5047c7c2 impl: Update PC when raising exception 2020-04-22 20:46:15 +01:00
MerryMage
49cc6d7fad A64: Implement FDIV (vector) 2020-04-22 20:46:15 +01:00
MerryMage
fd075d8d68 system: Raise exception for YIELD, WFE, WFI, SEV, SEVL 2020-04-22 20:46:15 +01:00
MerryMage
c832cec96d Correct FPSR and FPCR 2020-04-22 20:46:15 +01:00
MerryMage
147284427b A64: Implement USHL 2020-04-22 20:46:15 +01:00
MerryMage
fd8f4c1195 A64: Implement UCVTF (vector, integer), scalar variant 2020-04-22 20:46:15 +01:00
MerryMage
be57608353 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) 2020-04-22 20:46:15 +01:00
MerryMage
e4697b1676 A64: Implement system register TPIDR_EL0 2020-04-22 20:46:15 +01:00
MerryMage
e3da92024e A64: Implement system registers FPCR and FPSR 2020-04-22 20:46:15 +01:00
MerryMage
9e4e4e9c1d A64: Implement system register CNTPCT_EL0 2020-04-22 20:46:15 +01:00
MerryMage
1e15283d00 A64: Implement system register CTR_EL0 2020-04-22 20:46:15 +01:00
MerryMage
58fbb3ff1b A64: Implement NEG (vector) 2020-04-22 20:46:15 +01:00
MerryMage
710d09471b IR: Add IR instruction ZeroVector 2020-04-22 20:46:15 +01:00
MerryMage
0575e7421b A64: Implement FMINNM (scalar) 2020-04-22 20:46:15 +01:00
MerryMage
1c9804ea07 A64: Implement FMAXNM (scalar) 2020-04-22 20:46:15 +01:00
MerryMage
bd2b415850 A64: Implement ADDP (scalar) 2020-04-22 20:46:14 +01:00
MerryMage
9df3793af0 A64: Implement DUP (element), scalar variant 2020-04-22 20:46:14 +01:00
MerryMage
2080a51f41 A64: Implement FMAX (scalar), FMIN (scalar) 2020-04-22 20:46:14 +01:00