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  • 8cebb87d0d A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero) MerryMage 2018-02-13 19:01:21 +0000
  • 7f68d556ab decoder/a64: Rearrange SIMD two-register misc decoders MerryMage 2018-02-13 18:51:43 +0000
  • d5af052f06 A64: Implement CMGE (register) MerryMage 2018-02-13 18:29:54 +0000
  • 9d85991906 A64: Implement CMHI, CMHS MerryMage 2018-02-13 18:20:18 +0000
  • e2b9b7c5b0 IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned} MerryMage 2018-02-13 18:20:00 +0000
  • 0df6725f73 A64: Implement SMAX, SMIN, UMAX, UMIN MerryMage 2018-02-13 17:57:07 +0000
  • 47c0ad0fc8 IR: Implement Vector{Max,Min}{Signed,Unsigned} MerryMage 2018-02-13 17:56:46 +0000
  • adb7f5f86f A64: Implement CMGT (register) MerryMage 2018-02-13 14:07:09 +0000
  • f4775910f5 IR: Implement VectorGreaterSigned MerryMage 2018-02-13 14:06:54 +0000
  • 1f5b3bca43 Exclusive fixups MerryMage 2018-02-13 14:02:59 +0000
  • f3fa4a042f a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning) MerryMage 2018-02-13 12:59:31 +0000
  • 9f04f2c892 Merge branch 'feature/exclusive-mem' MerryMage 2018-02-13 12:53:13 +0000
  • 8698f057d0 A64: Implement STXP, STLXP, LDXP, LDAXP MerryMage 2018-02-13 12:50:50 +0000
  • 2a6619d59c A64: Implement CLREX MerryMage 2018-02-13 12:23:04 +0000
  • b7a2c1a7df A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR MerryMage 2018-02-13 00:19:04 +0000
  • f6a2104ab3 fuzz_with_unicorn: Speed up tests by not initializing/tearing down constantly MerryMage 2018-02-12 21:48:29 +0000
  • a38f35eef6 Merge branch 'feature/direct-page-table-access' MerryMage 2018-02-12 21:47:43 +0000
  • a6cc667509 Direct Page Table Access: Handle address spaces less than the full 64-bit in size MerryMage 2018-02-12 20:49:52 +0000
  • f45a5e17c6 Implement direct page table access MerryMage 2018-02-12 19:49:56 +0000
  • ef02658049 fuzz_with_unicorn: Fix read-past-end access via jit_iter MerryMage 2018-02-12 19:52:51 +0000
  • bfd3e30c75 callbacks: Member functions should be const MerryMage 2018-02-12 19:50:11 +0000
  • 9f2f08db8d a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call MerryMage 2018-02-12 18:18:47 +0000
  • 6c4773e85b abi: Add RAX to ABI_ALL_CALLER_SAVE MerryMage 2018-02-12 18:17:39 +0000
  • 8756487554 A64: Partially implement MRS MerryMage 2018-02-12 00:06:44 +0000
  • bfd65bedfe A64: Implement DSB, DMB MerryMage 2018-02-11 23:27:28 +0000
  • 5edd623b9d Implement DC instructions MerryMage 2018-02-11 22:53:46 +0000
  • a9153218bd A64: Implement NOT (vector) Lioncash 2018-02-11 14:16:47 -0500
  • 2cb0a699ba IR: Implement FPMax, FPMin MerryMage 2018-02-11 16:43:47 +0000
  • aed4fd3ec3 A64: Implement FADD (vector), vector variant MerryMage 2018-02-11 16:30:03 +0000
  • 98c8e7d1af IR: Implement FPVectorAdd MerryMage 2018-02-11 16:29:48 +0000
  • 5f77ab28ee A64: Implement SSHLL, SSHLL2 MerryMage 2018-02-11 16:24:55 +0000
  • eae518a338 IR: Implement VectorSignExtend MerryMage 2018-02-11 16:24:33 +0000
  • a90e4955ab CMakeLists: Ignore warnings within xbyak MerryMage 2018-02-11 14:57:35 +0000
  • 3738043e58 A64: Implement DUP (element), vector variant MerryMage 2018-02-11 14:34:13 +0000
  • ce7628b6b5 load_store_multiple_structures: Improve IR codegen for selem == 1 case MerryMage 2018-02-11 12:48:33 +0000
  • f1cb5581c9 A64: Implement FSUB (vector) MerryMage 2018-02-11 12:18:05 +0000
  • b9cd345ddc IR: Implement FPVectorSub MerryMage 2018-02-11 12:17:53 +0000
  • 851fc83445 emit_x64_vector: EmitOneArgumentFallback MerryMage 2018-02-11 11:58:39 +0000
  • f378d2ef1b Forward declare IR::Opcode and IR::Type where possible MerryMage 2018-02-11 11:46:18 +0000
  • 6c9b4f0114 A64: Implement CNT MerryMage 2018-02-11 11:44:00 +0000
  • 303088a51e IR: Implement VectorPopulationCount MerryMage 2018-02-11 11:43:51 +0000
  • 1dd2b33b87 A64: Implement MLS (vector) MerryMage 2018-02-11 11:04:46 +0000
  • 5eac3abf52 A64: Implement MLA (vector) MerryMage 2018-02-11 11:00:16 +0000
  • bf2cd92da9 emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64 MerryMage 2018-02-11 10:47:22 +0000
  • b062266b8e emit_x64_vector: More explicit lambda decay MerryMage 2018-02-11 10:47:00 +0000
  • 3afd2fcbad A64: Implement MUL (vector) MerryMage 2018-02-11 10:18:47 +0000
  • b6de612e01 IR: Implement VectorMultiply MerryMage 2018-02-11 10:18:29 +0000
  • 90a053a5e4 emit_x64_vector: Order alphabetically MerryMage 2018-02-11 09:41:37 +0000
  • e7041d7196 A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP) MerryMage 2018-02-11 01:06:26 +0000
  • a455ff70c9 decoder/a64: Don't rearrange unrelated decoders MerryMage 2018-02-11 00:04:59 +0000
  • faeb77e8c4 A64: Implement SUB (vector) MerryMage 2018-02-10 23:58:33 +0000
  • bd106c3ae7 A64: Implement SIMD instruction SSRA, vector variant MerryMage 2018-02-10 23:30:00 +0000
  • f58aba9871 A64: Implement SIMD instruction SSHR, vector variant MerryMage 2018-02-10 23:28:05 +0000
  • 715ae1c229 IR: Implement VectorArithmeticShiftRight MerryMage 2018-02-10 23:27:46 +0000
  • 653c82d8f0 impl: Improve Vpart setter MerryMage 2018-02-10 17:05:52 +0000
  • e858ce0b35 A64: Implement SIMD instructions XTN, XTN2 MerryMage 2018-02-10 16:47:50 +0000
  • 132c783320 IR: Implement VectorNarrow MerryMage 2018-02-10 16:47:36 +0000
  • 1423584f9f constant_pool: Allow for 128-bit constants MerryMage 2018-02-10 16:25:07 +0000
  • 69de50a878 emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend MerryMage 2018-02-10 16:24:43 +0000
  • cbc9f361b0 IR: Implement VectorSub MerryMage 2018-02-10 11:25:50 +0000
  • 3f93c77ace A64: Implement SIMD instruction USRA, vector variant MerryMage 2018-02-10 11:12:54 +0000
  • fb9d20f27f A64: Implement SIMD instruction USHR, vector variant MerryMage 2018-02-10 11:05:58 +0000
  • b22c5961f9 IR: Implement VectorLogicalShiftRight MerryMage 2018-02-10 11:05:22 +0000
  • 7ff280827b A64: Implement SIMD instructions USHLL, USHLL2 MerryMage 2018-02-10 10:29:07 +0000
  • 59ace60b03 IR: Implement VectorZeroExtend MerryMage 2018-02-10 10:28:38 +0000
  • d3a4e1efe2 IR: Vector instructions now take esize argument in emitter MerryMage 2018-02-10 10:18:10 +0000
  • 1d0cd95b23 A64: Implement SIMD instruction SHL MerryMage 2018-02-10 09:49:55 +0000
  • f6247125c0 IR: Implement VectorLogicalShiftLeft{8,16,32,64} MerryMage 2018-02-10 09:31:50 +0000
  • 15e8231f24 opcodes: Sort vector IR opcodes alphabetically MerryMage 2018-02-10 09:15:01 +0000
  • d74f4e35f6 block_of_code: Increase constant pool size MerryMage 2018-02-09 15:59:00 +0000
  • e69288f803 devirtualize: MinGW uses Intanium MFP ABI MerryMage 2018-02-09 15:58:44 +0000
  • ad428cbd7a callback: Properly handle calls with return pointers and simplify interface MerryMage 2018-02-09 15:58:16 +0000
  • 15871910af Implemented BSL, BIC, BIT and BIF vector instructions FernandoS27 2018-01-27 14:23:55 -0400
  • 7a87e3fc55 devirtualize: Handle Windows ABI MerryMage 2018-02-09 11:19:40 +0000
  • 12173a8792 travis: Switch to yuzu-emu's unicorn repository MerryMage 2018-02-08 19:48:04 +0000
  • a78e13ff19 fuzz_arm: Use SCOPE_FAIL MerryMage 2018-02-08 02:14:14 +0000
  • ba4a779c62 A32/decoder/arm: bug: Correct bitstring for SRS MerryMage 2018-02-08 02:05:49 +0000
  • f808a0fbde devirtualize: Devirtualize Itanium ABI MFPs at runtime MerryMage 2018-02-07 12:24:42 +0000
  • afe16fa0f3 cast_util: Add BitCast and BitCastPointee MerryMage 2018-02-07 12:22:35 +0000
  • 4e33629b0e A64: Move SDIV and UDIV out of data_processing_multiply.cpp Lioncash 2018-02-06 19:29:53 -0500
  • 35a29a9665 A64: Implement ZIP1 Lioncash 2018-02-04 22:29:14 -0500
  • 586854117b Implemented UMULH and SMULH instructions FernandoS27 2018-01-27 12:32:07 -0400
  • 1a7b7b541a A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate) MerryMage 2018-02-06 23:05:29 +0000
  • 8ab7d8175c impl: Add AdvSIMDExpandImm MerryMage 2018-02-06 23:04:23 +0000
  • ea69cb4474 A64: Implement SUB (vector), scalar variant MerryMage 2018-02-06 22:12:39 +0000
  • 4c5871d5d5 A64: Implement ADD (vector), scalar variant MerryMage 2018-02-06 22:09:39 +0000
  • 2a0850c068 A64: Reorganize decoder tables (some vector entries were grouped with scalar entries) MerryMage 2018-02-06 18:30:36 +0000
  • 7b33772ac6 A64: Implement BIC (vector, register) MerryMage 2018-02-06 17:57:50 +0000
  • ca43be4146 docs: Update documentation (2018-02-05) MerryMage 2018-02-05 22:30:39 +0000
  • eb5591859c A64: Implement FMOV (general) MerryMage 2018-02-05 21:44:20 +0000
  • dd88cee15a translate/impl: Add Vpart MerryMage 2018-02-05 21:43:58 +0000
  • cc9efd13c9 A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR MerryMage 2018-02-05 15:41:41 +0000
  • 81713c2b77 A64: Implement FCCMPE MerryMage 2018-02-05 12:25:53 +0000
  • ef906dbbfa A64: Implement FCCMP MerryMage 2018-02-05 12:25:04 +0000
  • 44c3c2312a a64_jitstate: Remove unnecessary FPSCR_nzcv member MerryMage 2018-02-05 12:23:51 +0000
  • aac5af50e2 IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them MerryMage 2018-02-05 12:16:01 +0000
  • 2ee39d6b36 A64: Implement FMOV (register) Lioncash 2018-02-04 21:43:06 -0500
  • b02b861242 A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR MerryMage 2018-02-05 01:10:52 +0000
  • 5a65313236 A64: Implement CCMP (immediate) Lioncash 2018-02-04 19:21:02 -0500
  • ab4664de61 A64: Implement CCMN (immediate) Lioncash 2018-02-04 19:17:36 -0500