MerryMage
|
7f68d556ab
|
decoder/a64: Rearrange SIMD two-register misc decoders
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
d5af052f06
|
A64: Implement CMGE (register)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
9d85991906
|
A64: Implement CMHI, CMHS
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e2b9b7c5b0
|
IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned}
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
0df6725f73
|
A64: Implement SMAX, SMIN, UMAX, UMIN
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
47c0ad0fc8
|
IR: Implement Vector{Max,Min}{Signed,Unsigned}
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
adb7f5f86f
|
A64: Implement CMGT (register)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f4775910f5
|
IR: Implement VectorGreaterSigned
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
1f5b3bca43
|
Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f3fa4a042f
|
a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
8698f057d0
|
A64: Implement STXP, STLXP, LDXP, LDAXP
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
2a6619d59c
|
A64: Implement CLREX
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b7a2c1a7df
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a6cc667509
|
Direct Page Table Access: Handle address spaces less than the full 64-bit in size
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f45a5e17c6
|
Implement direct page table access
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bfd3e30c75
|
callbacks: Member functions should be const
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
9f2f08db8d
|
a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
6c4773e85b
|
abi: Add RAX to ABI_ALL_CALLER_SAVE
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
8756487554
|
A64: Partially implement MRS
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bfd65bedfe
|
A64: Implement DSB, DMB
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5edd623b9d
|
Implement DC instructions
|
2020-04-22 20:46:14 +01:00 |
|
Lioncash
|
a9153218bd
|
A64: Implement NOT (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
2cb0a699ba
|
IR: Implement FPMax, FPMin
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
aed4fd3ec3
|
A64: Implement FADD (vector), vector variant
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
98c8e7d1af
|
IR: Implement FPVectorAdd
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5f77ab28ee
|
A64: Implement SSHLL, SSHLL2
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
eae518a338
|
IR: Implement VectorSignExtend
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
3738043e58
|
A64: Implement DUP (element), vector variant
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
ce7628b6b5
|
load_store_multiple_structures: Improve IR codegen for selem == 1 case
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f1cb5581c9
|
A64: Implement FSUB (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b9cd345ddc
|
IR: Implement FPVectorSub
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
851fc83445
|
emit_x64_vector: EmitOneArgumentFallback
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f378d2ef1b
|
Forward declare IR::Opcode and IR::Type where possible
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
6c9b4f0114
|
A64: Implement CNT
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
303088a51e
|
IR: Implement VectorPopulationCount
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
1dd2b33b87
|
A64: Implement MLS (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5eac3abf52
|
A64: Implement MLA (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bf2cd92da9
|
emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b062266b8e
|
emit_x64_vector: More explicit lambda decay
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
3afd2fcbad
|
A64: Implement MUL (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b6de612e01
|
IR: Implement VectorMultiply
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
90a053a5e4
|
emit_x64_vector: Order alphabetically
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e7041d7196
|
A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a455ff70c9
|
decoder/a64: Don't rearrange unrelated decoders
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
faeb77e8c4
|
A64: Implement SUB (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bd106c3ae7
|
A64: Implement SIMD instruction SSRA, vector variant
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f58aba9871
|
A64: Implement SIMD instruction SSHR, vector variant
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
715ae1c229
|
IR: Implement VectorArithmeticShiftRight
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
653c82d8f0
|
impl: Improve Vpart setter
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e858ce0b35
|
A64: Implement SIMD instructions XTN, XTN2
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
132c783320
|
IR: Implement VectorNarrow
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1423584f9f
|
constant_pool: Allow for 128-bit constants
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
69de50a878
|
emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
cbc9f361b0
|
IR: Implement VectorSub
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
3f93c77ace
|
A64: Implement SIMD instruction USRA, vector variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
fb9d20f27f
|
A64: Implement SIMD instruction USHR, vector variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
b22c5961f9
|
IR: Implement VectorLogicalShiftRight
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7ff280827b
|
A64: Implement SIMD instructions USHLL, USHLL2
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
59ace60b03
|
IR: Implement VectorZeroExtend
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
d3a4e1efe2
|
IR: Vector instructions now take esize argument in emitter
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1d0cd95b23
|
A64: Implement SIMD instruction SHL
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
f6247125c0
|
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
15e8231f24
|
opcodes: Sort vector IR opcodes alphabetically
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
d74f4e35f6
|
block_of_code: Increase constant pool size
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
e69288f803
|
devirtualize: MinGW uses Intanium MFP ABI
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ad428cbd7a
|
callback: Properly handle calls with return pointers and simplify interface
|
2020-04-22 20:46:13 +01:00 |
|
FernandoS27
|
15871910af
|
Implemented BSL, BIC, BIT and BIF vector instructions
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7a87e3fc55
|
devirtualize: Handle Windows ABI
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ba4a779c62
|
A32/decoder/arm: bug: Correct bitstring for SRS
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
f808a0fbde
|
devirtualize: Devirtualize Itanium ABI MFPs at runtime
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
afe16fa0f3
|
cast_util: Add BitCast and BitCastPointee
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
4e33629b0e
|
A64: Move SDIV and UDIV out of data_processing_multiply.cpp
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
35a29a9665
|
A64: Implement ZIP1
|
2020-04-22 20:46:13 +01:00 |
|
FernandoS27
|
586854117b
|
Implemented UMULH and SMULH instructions
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1a7b7b541a
|
A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
8ab7d8175c
|
impl: Add AdvSIMDExpandImm
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ea69cb4474
|
A64: Implement SUB (vector), scalar variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4c5871d5d5
|
A64: Implement ADD (vector), scalar variant
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
2a0850c068
|
A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7b33772ac6
|
A64: Implement BIC (vector, register)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
eb5591859c
|
A64: Implement FMOV (general)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
dd88cee15a
|
translate/impl: Add Vpart
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
cc9efd13c9
|
A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
81713c2b77
|
A64: Implement FCCMPE
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ef906dbbfa
|
A64: Implement FCCMP
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
44c3c2312a
|
a64_jitstate: Remove unnecessary FPSCR_nzcv member
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
aac5af50e2
|
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
2ee39d6b36
|
A64: Implement FMOV (register)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
b02b861242
|
A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
5a65313236
|
A64: Implement CCMP (immediate)
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ab4664de61
|
A64: Implement CCMN (immediate)
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
a6c6539109
|
A64: Implement CCMP (register)
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
22632db337
|
microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
c5033b5dda
|
A64: Implement CCMN (register)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
dd2a6684fe
|
IR: Add ConditionalSelectNZCV instruction
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4491746eae
|
A64: Implement FNEG
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
db958061a3
|
A64: Implement FABS
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
8765b421b7
|
A64: Implement FCSEL
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7e82d8eede
|
A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
2409e5d082
|
A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
b173fcf34e
|
backend_x64: Simplify FPDoubleToU32 and FPSingleToU32
They're inaccurate in terms of FPSR at the moment anyway.
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
56bc7825ef
|
A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
d040920727
|
Common: Put AES code within its own nested namespace
Prevents the functions from potentially clashing with other stuff in Common in the future
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
40614202e7
|
A64: Implement AESD
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ccef85dbb7
|
A64: Implement AESE
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
68f46c8334
|
backend_x64: Use a reference to BlockOfCode instead of a pointer
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
8931ee346b
|
IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
0bb4474fb9
|
A64: Implement INS (general)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
d13704fdef
|
A64: Implement INS (element)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
0642d49919
|
A64: Implement SMOV
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
5297027ebe
|
A64: Implement UMOV
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
47661b746b
|
basic_block: Fix bogus GCC maybe-uninitialized warning
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1fb0957aa3
|
A64: Implement FCVT
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ca38225e08
|
fuzz_with_unicorn: Skip instructions that need to be interpreted
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4be55b8b84
|
A64: Implement FMOV (scalar, immediate)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
a07c05ea51
|
A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
93fcbdf1e2
|
A64: Implement FCMP, FCMPE
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
75b8a76630
|
a64_jitstate: A64 does not have a seperate FPSCR.NZCV
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
99d8ebe4d5
|
A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
429dc24587
|
IR: Merge U32 and U64 variants of FP instructions
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ed2bedec43
|
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
6414736a8d
|
emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1
This bug wasn't discovered earlier because we previously only used index == 0.
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ebfc51c609
|
IR: Implement VectorSetElement{8,16,32,64}
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
a5c4fbc783
|
A64: Implement AESIMC and AESMC
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
744495e23d
|
iterator_util: Make Reverse constexpr
C++17 makes non-member rbegin(), rend(), crbegin(), and crend() constexpr, allowing this to also be constexpr.
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
ab9b5fb8aa
|
Common: Relocate common bits of CRC32
Allows the algorithm to be used in any other potential backend.
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
af1384d700
|
A64: Implement CRC32
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
64761dbc72
|
scope_exit: Add SCOPE_SUCCESS and SCOPE_EXIT
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
bafb39ebc5
|
A64: Add Disassemble method
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
cc0eb18a0b
|
A32: data_processing: Remove !S assertions
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
865a30eb0d
|
A32: Implement BKPT
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
f023bbb893
|
A32: Add ExceptionRaised IR instruction and use it
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
7ffbebf290
|
A64: Implement CRC32C
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
d7044bc751
|
assert: Use fmt in ASSERT_MSG
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
52268298a8
|
a64_emit_x64: Perform RSB predictions
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
98ec9c5f90
|
A32: Change UserCallbacks to be similar to A64's interface
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
b9ce660113
|
reg_alloc: std::move RegAlloc's function argument
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
ed561d6653
|
General: Add missing override specifiers
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
b2d99eddc6
|
EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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f4f774f9f6
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a64_get_set_elimination_pass: Simplify algorithm
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
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54de64f5bf
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a64_emit_x64: bug: x64 sign-extends 32-bit immediates
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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6fc228f7fd
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ir_opt: Add A64 Get/Set Elimination Pass
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
e01b500aea
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ir_emitter: Allow the insertion point for new instructions to be set
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
af793c2527
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{a32,a64}_interface: Predict entrypoint
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2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
7734cf1050
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A64: Implement EXTR
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
88ae7fce52
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A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
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2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
d497464c9f
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a64_jitstate: Have 128-bit wide spills
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2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
b513b2ef05
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IR: Implement IR instructions A64{Get,Set}S
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2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
16fa2cd8f6
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a64_emit_x64: Use xword from Xbyak::util
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2020-04-22 20:44:38 +01:00 |
|
Lioncash
|
67443efb62
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
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2020-04-22 20:44:38 +01:00 |
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