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607 commits

Author SHA1 Message Date
Lioncash
2db032ac83 A64: Implement SRI (vector) 2020-04-22 20:46:16 +01:00
Lioncash
11005cfe26 A64: Implement SLI (vector) 2020-04-22 20:46:16 +01:00
Lioncash
e3d9bf55e7 A64: Implement SRSRA (vector) 2020-04-22 20:46:16 +01:00
Lioncash
bc6016cad7 A64: Implement SRSHR (vector) 2020-04-22 20:46:16 +01:00
MerryMage
6c9c829a08 imm: Add additional bit position checks to Imm::Bits 2020-04-22 20:46:16 +01:00
Lioncash
a2f8cdf0a3 A64: Implement SSUBL/SSUBL2 2020-04-22 20:46:16 +01:00
Lioncash
d456fb85c8 A64: Implement SADDL/SADDL2 2020-04-22 20:46:16 +01:00
Lioncash
5c9e7f328d A64: Implement USUBL/USUBL2 2020-04-22 20:46:16 +01:00
Lioncash
88d70e3b8a A64: Implement UADDL/UADDL2 2020-04-22 20:46:16 +01:00
Lioncash
4b3d70de5f simd_shift_by_immediate: Factor out common code in shift instructions 
Gets rid of partial duplication of the same code for instructions that only have a small behavior difference to them.

e.g. The only difference between SSHR and SSRA is that SSRA adds an accumulator before storing the result.
 2020-04-22 20:46:16 +01:00
Lioncash
56803f5203 A64: Implement URSRA (vector) 2020-04-22 20:46:16 +01:00
Lioncash
8afdf4b23d A64: Implement URSHR (vector) 2020-04-22 20:46:16 +01:00
Lioncash
16613ee066 A64: Implement RSHRN/RSHRN2 2020-04-22 20:46:15 +01:00
Lioncash
937990fd2a A64: Implement SHRN/SHRN2 2020-04-22 20:46:15 +01:00
Lioncash
80e005e5b5 A64/translate: Amend I() to also handle u8 and u16 immediates 
This is necessary for instructions like SRSHR, and other related instructions.
 2020-04-22 20:46:15 +01:00
MerryMage
7969871aa3 A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated 2020-04-22 20:46:15 +01:00
MerryMage
5c95e28ed0 A64: Implement ZIP2 2020-04-22 20:46:15 +01:00
MerryMage
871aefb9a0 decoder/a64: Tweak ordering algorithm 
Ensuring only instruction families are sorted with each other in
the fashion previously devised does not admit a total ordering.
 2020-04-22 20:46:15 +01:00
MerryMage
575590d18d ir_emitter: Remove overloads 
Having overloads made explicit casting necesssary for these functions when
using types like UAny.
 2020-04-22 20:46:15 +01:00
Lioncash
83ff7a43d1 A64: Implement RBIT (vector) 2020-04-22 20:46:15 +01:00
Lioncash
64b1f2d468 ir: Add opcode for reversing bits in a vector 2020-04-22 20:46:15 +01:00
Lioncash
9de60b60bb A64/translate: Amend instruction prototypes erroneously marked as taking Reg 
Makes the prototypes consistent
 2020-04-22 20:46:15 +01:00
Lioncash
cf81f04ed3 A64: Implement RAX1 2020-04-22 20:46:15 +01:00
Lioncash
7bcb1c115a A64: Implement ABS (vector) 2020-04-22 20:46:15 +01:00
Lioncash
e33dcce14a ir: Add opcodes for performing vector absolute values 2020-04-22 20:46:15 +01:00
Lioncash
84d49309b9 A64: Implement USUBW/USUBW2 2020-04-22 20:46:15 +01:00
Lioncash
e20fce6b5a A64: Implement SSUBW/SSUBW2 2020-04-22 20:46:15 +01:00
Lioncash
00af6eeab9 A64: Implement SADDW/SADDW2 2020-04-22 20:46:15 +01:00
MerryMage
78a047f0f9 A64: Implement EXT 2020-04-22 20:46:15 +01:00
MerryMage
3472f371df IR: Implement VectorExtract, VectorExtractLower IR instructions 2020-04-22 20:46:15 +01:00
MerryMage
8bba37089e A64: Implement UADDW 2020-04-22 20:46:15 +01:00
MerryMage
5c47f03888 A64: Implement FMUL (vector) 2020-04-22 20:46:15 +01:00
Lioncash
a6e264c2dd A64: Implement UABA 
Now that we have unsigned absolute difference capabilities, we can just use this to
append onto the result via a vector add.
 2020-04-22 20:46:15 +01:00
Lioncash
c2e7364d3e A64: Implement UABD 2020-04-22 20:46:15 +01:00
Lioncash
ad5cf584ce ir: Add opcodes for performing vector unsigned absolute differences 2020-04-22 20:46:15 +01:00
Lioncash
7780af56e3 ir_emitter: Make immediate member functions const qualified 
These don't modify class state
 2020-04-22 20:46:15 +01:00
Lioncash
701f43d61e IR: Add opcodes for interleaving upper-order bytes/halfwords/words/doublewords 
I should have added this when I introduced the functions for interleaving
low-order equivalents for consistency in the interface.
 2020-04-22 20:46:15 +01:00
Lioncash
94f0fba16b A64: Implement SHA1H 
This is a fairly trivial instruction it's essentially:

result = ROL(data, 30);
 2020-04-22 20:46:15 +01:00
Lioncash
40ec25356b A64: NOP immediate variant of PRFM 
Makes behavior identical to the literal variant of PRFM. Given this is simply a hint instruction,
this is valid behavior. The upside is that we don't fall back to Unicorn unnecessarily whenever
the instruction is encountered.
 2020-04-22 20:46:15 +01:00
Lioncash
73b9e4b276 A64: system: Use an enum class for MRS/MSR register encodings 
Reduces the need to manually write out the register bit encodings repeatedly.
 2020-04-22 20:46:15 +01:00
Lioncash
586b00d11d A64: Implement REV64 2020-04-22 20:46:15 +01:00
Lioncash
9128988dc3 A64: Implement REV32 (vector) 2020-04-22 20:46:15 +01:00
Lioncash
6b0010c940 ir: Add IR opcodes for emitting vector shuffles 
This uses the ARM terminology for sizes (Halfword -> 2 bytes, Word -> 4 bytes)
as opposed to the x86 terminology of (Word -> 2 bytes, Double word -> 4 bytes)
 2020-04-22 20:46:15 +01:00
Lioncash
6ad1bce5e0 A64: Implement REV16 (vector) 2020-04-22 20:46:15 +01:00
Lioncash
7a66224d9a A64: Implement EOR3 and BCAX 2020-04-22 20:46:15 +01:00
MerryMage
be5047c7c2 impl: Update PC when raising exception 2020-04-22 20:46:15 +01:00
MerryMage
49cc6d7fad A64: Implement FDIV (vector) 2020-04-22 20:46:15 +01:00
MerryMage
fd075d8d68 system: Raise exception for YIELD, WFE, WFI, SEV, SEVL 2020-04-22 20:46:15 +01:00
MerryMage
c832cec96d Correct FPSR and FPCR 2020-04-22 20:46:15 +01:00
MerryMage
147284427b A64: Implement USHL 2020-04-22 20:46:15 +01:00
MerryMage
fd8f4c1195 A64: Implement UCVTF (vector, integer), scalar variant 2020-04-22 20:46:15 +01:00
MerryMage
be57608353 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) 2020-04-22 20:46:15 +01:00
MerryMage
e4697b1676 A64: Implement system register TPIDR_EL0 2020-04-22 20:46:15 +01:00
MerryMage
e3da92024e A64: Implement system registers FPCR and FPSR 2020-04-22 20:46:15 +01:00
MerryMage
9e4e4e9c1d A64: Implement system register CNTPCT_EL0 2020-04-22 20:46:15 +01:00
MerryMage
1e15283d00 A64: Implement system register CTR_EL0 2020-04-22 20:46:15 +01:00
MerryMage
58fbb3ff1b A64: Implement NEG (vector) 2020-04-22 20:46:15 +01:00
MerryMage
710d09471b IR: Add IR instruction ZeroVector 2020-04-22 20:46:15 +01:00
MerryMage
0575e7421b A64: Implement FMINNM (scalar) 2020-04-22 20:46:15 +01:00
MerryMage
1c9804ea07 A64: Implement FMAXNM (scalar) 2020-04-22 20:46:15 +01:00
MerryMage
bd2b415850 A64: Implement ADDP (scalar) 2020-04-22 20:46:14 +01:00
MerryMage
9df3793af0 A64: Implement DUP (element), scalar variant 2020-04-22 20:46:14 +01:00
MerryMage
2080a51f41 A64: Implement FMAX (scalar), FMIN (scalar) 2020-04-22 20:46:14 +01:00
MerryMage
0e157b0198 A64: Implement FSQRT (scalar) 2020-04-22 20:46:14 +01:00
MerryMage
01c1e9017e T32: Add initial decoder list 2020-04-22 20:46:14 +01:00
MerryMage
ccf7df057b simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector) 2020-04-22 20:46:14 +01:00
MerryMage
8cebb87d0d A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero) 2020-04-22 20:46:14 +01:00
MerryMage
7f68d556ab decoder/a64: Rearrange SIMD two-register misc decoders 2020-04-22 20:46:14 +01:00
MerryMage
d5af052f06 A64: Implement CMGE (register) 2020-04-22 20:46:14 +01:00
MerryMage
9d85991906 A64: Implement CMHI, CMHS 2020-04-22 20:46:14 +01:00
MerryMage
e2b9b7c5b0 IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned} 2020-04-22 20:46:14 +01:00
MerryMage
0df6725f73 A64: Implement SMAX, SMIN, UMAX, UMIN 2020-04-22 20:46:14 +01:00
MerryMage
47c0ad0fc8 IR: Implement Vector{Max,Min}{Signed,Unsigned} 2020-04-22 20:46:14 +01:00
MerryMage
adb7f5f86f A64: Implement CMGT (register) 2020-04-22 20:46:14 +01:00
MerryMage
f4775910f5 IR: Implement VectorGreaterSigned 2020-04-22 20:46:14 +01:00
MerryMage
1f5b3bca43 Exclusive fixups 
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
 2020-04-22 20:46:14 +01:00
MerryMage
8698f057d0 A64: Implement STXP, STLXP, LDXP, LDAXP 2020-04-22 20:46:14 +01:00
MerryMage
2a6619d59c A64: Implement CLREX 2020-04-22 20:46:14 +01:00
MerryMage
b7a2c1a7df A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR 2020-04-22 20:46:14 +01:00
MerryMage
8756487554 A64: Partially implement MRS 2020-04-22 20:46:14 +01:00
MerryMage
bfd65bedfe A64: Implement DSB, DMB 2020-04-22 20:46:14 +01:00
MerryMage
5edd623b9d Implement DC instructions 2020-04-22 20:46:14 +01:00
Lioncash
a9153218bd A64: Implement NOT (vector) 2020-04-22 20:46:14 +01:00
MerryMage
2cb0a699ba IR: Implement FPMax, FPMin 2020-04-22 20:46:14 +01:00
MerryMage
aed4fd3ec3 A64: Implement FADD (vector), vector variant 2020-04-22 20:46:14 +01:00
MerryMage
98c8e7d1af IR: Implement FPVectorAdd 2020-04-22 20:46:14 +01:00
MerryMage
5f77ab28ee A64: Implement SSHLL, SSHLL2 2020-04-22 20:46:14 +01:00
MerryMage
eae518a338 IR: Implement VectorSignExtend 2020-04-22 20:46:14 +01:00
MerryMage
3738043e58 A64: Implement DUP (element), vector variant 2020-04-22 20:46:14 +01:00
MerryMage
ce7628b6b5 load_store_multiple_structures: Improve IR codegen for selem == 1 case 2020-04-22 20:46:14 +01:00
MerryMage
f1cb5581c9 A64: Implement FSUB (vector) 2020-04-22 20:46:14 +01:00
MerryMage
b9cd345ddc IR: Implement FPVectorSub 2020-04-22 20:46:14 +01:00
MerryMage
f378d2ef1b Forward declare IR::Opcode and IR::Type where possible 2020-04-22 20:46:14 +01:00
MerryMage
6c9b4f0114 A64: Implement CNT 2020-04-22 20:46:14 +01:00
MerryMage
303088a51e IR: Implement VectorPopulationCount 2020-04-22 20:46:14 +01:00
MerryMage
1dd2b33b87 A64: Implement MLS (vector) 2020-04-22 20:46:14 +01:00
MerryMage
5eac3abf52 A64: Implement MLA (vector) 2020-04-22 20:46:14 +01:00
MerryMage
3afd2fcbad A64: Implement MUL (vector) 2020-04-22 20:46:14 +01:00
MerryMage
b6de612e01 IR: Implement VectorMultiply 2020-04-22 20:46:14 +01:00
MerryMage
e7041d7196 A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP) 2020-04-22 20:46:14 +01:00