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1445 commits

Author SHA1 Message Date
MerryMage
3e252cdbfc VFPv5: Implement VSEL 2020-06-19 19:44:45 +01:00
MerryMage
669d05caca VFPv5: Implement VMINNM 2020-06-19 19:44:45 +01:00
MerryMage
6e7ea151a3 VFPv5: Implement VMAXNM 2020-06-19 19:39:01 +01:00
MerryMage
4df3b2f97f vfp: Add decoders for VFPv5 
These instructions were introduced in the Cortex-M7
 2020-06-19 19:24:32 +01:00
Lioncash
551e207661 A32: Implement ASIMD VSUB (integer) 2020-06-19 11:31:38 +01:00
Lioncash
4d6f68525d A32: Implement ASIMD VADD (integer) 2020-06-19 11:31:38 +01:00
Lioncash
fbdae61c13 A32: Implement ASIMD VMVN (register) 
Fairly straightforward
 2020-06-19 11:31:14 +01:00
merry
687c604197
Merge pull request #532 from lioncash/shift 
A32: Implement several ASIMD shift instructions
 2020-06-19 00:22:18 +01:00
Lioncash
00b2f9b319 asimd: Prevent misdecodes from occurring 
Pointed out by Mary when reviewing the shift code.
 2020-06-18 15:04:48 -04:00
MerryMage
d34763242c Revert "A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero" 
This reverts commit 179951b10f.

These instructions require StandardFPSCRValue.
 2020-06-18 17:38:40 +01:00
Lioncash
179951b10f A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero 
Fairly self-explanatory, we can leverage the existing IR functions for
the purpose of these instructions.

In the integer case, we can just insert function pointers
into an array and index it, given all comparison primitives exist
already for the integer side of things.
 2020-06-18 17:01:57 +01:00
Lioncash
6ca20c2fe3 A32: Implement ASIMD VSLI 2020-06-18 11:51:08 -04:00
Lioncash
887732d8a8 A32: Implement ASIMD VSRI 2020-06-18 11:28:12 -04:00
Lioncash
8b98c91ecc A32: Implement ASIMD VSHL 2020-06-18 11:18:33 -04:00
Lioncash
69c999bc66 A32: Implement ASIMD VRSRA 
Now that we have the accumulation and rounding code in place, VRSRA is
extremely trivial to implement.
 2020-06-18 11:03:39 -04:00
Lioncash
14fdd15199 A32: Implement ASIMD VRSHR 2020-06-18 11:00:45 -04:00
Lioncash
276e0b71dc A32: Implement ASIMD VSRA 2020-06-18 11:00:27 -04:00
Lioncash
054dff7cd5 A32: Implement ASIMD VTST 2020-06-18 15:34:05 +01:00
Lioncash
6c142bc5cc A32: Implement ASIMD VSHR 2020-06-18 10:30:20 -04:00
Lioncash
08350d06f1 A32: Implement ASIMD VQNEG 2020-06-18 09:49:29 +01:00
Lioncash
f6b665f5a4 A32: Implement ASIMD VQABS 2020-06-18 09:49:29 +01:00
Lioncash
4b371c0445 A32: Implement ASIMD VREV{16, 32, 64} 2020-06-17 10:21:59 +01:00
Lioncash
6dd2c94095 A32: Implement ASIMD VABS 
Very similar to VNEG in that the only thing that differs is the function
called.
 2020-06-16 22:42:18 +01:00
MerryMage
2c1a4843ad A32 global exlcusive monitor 2020-06-16 17:54:21 +01:00
MerryMage
7ea521b8bf a32_emit_x64: Change ExclusiveWriteMemory64 to require a single U64 argument 2020-06-16 13:32:50 +01:00
Lioncash
aabd0d824d A32: Add immediate creation helper 
Provides the same helper function that exists within the A64 frontend
for creating immediate values.
 2020-06-16 09:54:28 +01:00
Lioncash
93ed3441b7 A32: Implement ASIMD VCLS/VCLZ/VCNT 2020-06-16 09:54:28 +01:00
Lioncash
15b3de95e4 A32: Implement VNEG 2020-06-16 01:53:21 +01:00
MerryMage
bb203429c6 crc32: Remove unnecessary masking 2020-06-04 20:33:46 +01:00
MerryMage
f3845cea9a A32: Implement ASIMD VQSUB instruction 2020-05-30 18:19:17 +01:00
MerryMage
16ff880f8f A32: Implement ASIMD VQADD 2020-05-30 16:09:37 +01:00
MerryMage
174fbb74c5 simd_three_same: Use VectorSaturated{Signed,Unsigned}{Add,Sub} in SaturatingArithmeticOperation 2020-05-30 15:55:32 +01:00
MerryMage
4e90754873 IR: Implement VectorSaturated{Signed,Unsigned}{Add,Sub} 2020-05-30 15:55:32 +01:00
MerryMage
3a50d444dc A32: Implement ASIMD VHSUB 2020-05-28 22:29:00 +01:00
MerryMage
205e6c5a56 A32: Implement ASIMD VRHADD 2020-05-28 22:29:00 +01:00
MerryMage
946eb03a3b A32: Implement ASIMD VHADD 2020-05-28 22:29:00 +01:00
MerryMage
f8062345bb asimd_two_regs_misc: Use {Get,Set}Vector 2020-05-28 21:05:30 +01:00
MerryMage
11cec1e3b6 asimd_three_same: Use {Get,Set}Vector 2020-05-28 21:05:16 +01:00
MerryMage
7d0b16de32 asimd_one_reg_modified_immediate: Use {Get,Set}Vector 2020-05-28 20:40:26 +01:00
MerryMage
ebddf6cca0 basic_block: Allow printing of invalid instruction pointers 2020-05-28 20:39:50 +01:00
MerryMage
07108246cf A32/IR: Add SetVector and GetVector 2020-05-28 20:39:19 +01:00
Lioncash
c4a4bdd7de frontend: Relocate ExtReg handling to types.h 
Same behavior, but deduplicates the code being placed across several
files
 2020-05-24 23:55:47 +01:00
Lioncash
1900df5340 frontend: Relocate advanced SIMD expansion to a common file 
Deduplicates code a little bit.
 2020-05-24 23:55:47 +01:00
Lioncash
fc112e61f2 A32: Implement ASIMD modified immediate functions 
Implements VBIC, VMOV, VMVN, and VORR modified immediate instructions.
 2020-05-24 23:55:47 +01:00
Lioncash
659d78c9c4 A32: Implement ASIMD VSWP 
A trivial one to implement, this just swaps the contents of two
registers in place.
 2020-05-22 19:43:24 +01:00
MerryMage
c59a127e86 opcodes: Switch from std::map to std::array 
Optimization.
 2020-05-17 17:01:39 +01:00
MerryMage
d0b45f6150 A32: Implement ARMv8 VST{1-4} (multiple) 2020-05-17 17:01:39 +01:00
Lioncash
eb332b3836 asimd_three_same: Unify BitwiseInstructionWithDst with BitwiseInstruction 
Now that all bitwise instructions are implemented, we can unify all of
them together using if constexpr.
 2020-05-16 20:22:12 +01:00
Lioncash
f42b3ad4a0 A32: Implement ASIMD VBIF (register) 2020-05-16 20:22:12 +01:00
Lioncash
ee9a81dcba A32: Implement ASIMD VBIT (register) 2020-05-16 20:22:12 +01:00
Lioncash
d624059ead A32: Implement ASIMD VBSL (register) 2020-05-16 20:22:12 +01:00
Lioncash
66663cf8e7 asimd_three_same: Collapse all bitwise implementations into a single code path 
Less code and results in only writing the parts that matter once.
 2020-05-16 20:22:12 +01:00
Lioncash
4b5e3437cf A32: Implement ASIMD VEOR (register) 2020-05-16 20:22:12 +01:00
Lioncash
67b284f6fa A32: Implement ASIMD VORN (register) 2020-05-16 20:22:12 +01:00
Lioncash
1fdd90ca2a A32: Implement ASIMD VORR (register) 2020-05-16 20:22:12 +01:00
Lioncash
64fa804dd4 A32: Implement ASIMD VBIC (register) 2020-05-16 20:22:12 +01:00
Lioncash
0441ab81a1 A32: Implement ASIMD VAND (register) 2020-05-16 20:22:12 +01:00
Lioncash
1b25e867ae asimd_load_store_structures: Simplify ToExtRegD() 
ExtReg has a supplied operator+, so we can make use of that instead.
 2020-05-16 11:27:22 -04:00
MerryMage
1a0bc5ba91 A32/ASIMD: ARMv8: Implement VLD{1-4} (multiple) 2020-05-16 14:11:23 +01:00
MerryMage
e7f1a0d408 A32: ARMv8: Implement LDA{,EX}{,B,D,H} and STL{,EX}{,B,D,H} 2020-05-15 21:07:36 +01:00
Lioncash
af3b65b135 decoder_detail: Mark GetMaskAndExpect() as constexpr 
Elides quite a bit of code at runtime when constructing the decoding
tables.
 2020-05-11 08:29:06 +01:00
MerryMage
59db2c191a VFPv3: Implement VMOV (immediate) 2020-05-10 15:09:37 +01:00
MerryMage
3c86d58064 VFPv4: Implement VCVTB, VCVTT 2020-05-10 14:45:18 +01:00
MerryMage
010fab9a0e VFPv4: Implement VFMA, VFMS 2020-05-10 14:20:11 +01:00
MerryMage
8e97b10acb VFPv4: Implement VFNMS, VFNMA 2020-05-10 14:14:03 +01:00
MerryMage
6df660c889 fuzz_arm: Ensure all instructions are fuzzed 
* VFP instructions were not getting fuzzed due to matching coprocessor instructions (as invalid instructions)
* Fix VPOP writeback for doubles when (imm8 & 1) == 1
* Do not accidentally fuzz unimplemented unconditional instructions
 2020-05-10 13:57:39 +01:00
MerryMage
9a38c7324f A32: Add decoders for remaining v7 instructions 2020-05-10 10:50:34 +01:00
Fernando Sahmkow
41521ed856 User Config: Add option to specify wall clock CNTPCT. 2020-05-03 01:40:37 +01:00
Fernando Sahmkow
97b9d3e058 Exclusive Monitor: Rework exclusive monitor interface. 2020-05-03 01:40:37 +01:00
MerryMage
dca983803a translate_arm: ConditionPassed: Some instructions emit no microinstructions 2020-04-24 13:12:13 +01:00
MerryMage
94d0d33e02 Fix single stepping for certain instructions 
Several issues:
1. Several terminal instructions did not stop at the end of a single-step block
2. x64 backend for the A32 frontend sometimes polluted upper_location_descriptor with the single-stepping flag

We also introduce the enable_optimizations parameter to the A32 frontend.
 2020-04-24 11:44:38 +01:00
MerryMage
5c0bb5cc63 Remove unreachable code (MSVC warnings) 2020-04-23 16:36:34 +01:00
MerryMage
a8a712c801 Relicense to 0BSD 2020-04-23 15:45:57 +01:00
MerryMage
7242388577 A64: Specialize arithmetic shift SBFM aliases 2020-04-22 21:07:09 +01:00
MerryMage
a13392e432 A64: Specialize sign-extension SBFM aliases 2020-04-22 21:07:09 +01:00
MerryMage
4573511fe3 constant_propagation_pass: Prepare for IR matchers 2020-04-22 21:07:09 +01:00
MerryMage
0d7476d3ec constant_propagation_pass: Propagate constants across commutative operations 
e.g. (a & b) & c == a & (b & c) where b and c are constants
 2020-04-22 21:07:09 +01:00
MerryMage
f59b9fb020 IR: Add ReplicateBit microinstruction 2020-04-22 21:07:09 +01:00
MerryMage
93adcfa5c6 value: Add GetInstRecursive 2020-04-22 21:06:18 +01:00
MerryMage
2ae68b13ed value: Add IsIdentity function 2020-04-22 21:06:18 +01:00
MerryMage
8db4d65587 A64/decoder: Use a lookup table instead of doing a linear scan 2020-04-22 21:06:18 +01:00
MerryMage
668a43f815 A32: Detect unpredictable LDM/STM instructions 2020-04-22 21:06:18 +01:00
MerryMage
4636055646 a32_emit_x64: Implement fastmem 2020-04-22 21:06:17 +01:00
MerryMage
b6536115ef A32: Add Step 2020-04-22 21:06:17 +01:00
MerryMage
f69c77391e A64: Add Step 
Allow for stepping instruction-by-instruction
 2020-04-22 21:06:17 +01:00
MerryMage
09d3c77d74 IR: Add masked shift IR instructions 
Also use these in the A64 frontend to avoid the need to mask the shift amount.
 2020-04-22 21:06:17 +01:00
MerryMage
81fcb4e537 mp: Migrate to shared version of mp library 2020-04-22 21:06:17 +01:00
MerryMage
e10985d179 ir/basic_block: Add FastDispatchHint to TerminalToString 
Use a boost::static_visitor to ensure this is caught at compile-time in the future.
 2020-04-22 21:04:23 +01:00
Lioncash
af3614553b A64/impl: Move AccType and MemOp enum into general IR emitter header 
These will be used by both frontends in the future, so this performs the
migratory changes separate from the changes that will make use of them.
 2020-04-22 21:04:23 +01:00
MerryMage
1aa7b62e92 A32/Thumb: Correct behaviour for UDF and Unpredictable instructions 
Raise an exception instead of calling the interpreter and ASSERT-ing respectively.
 2020-04-22 21:04:23 +01:00
MerryMage
717bd2fbb2 A64: Add hook_hint_instructions option 2020-04-22 21:04:23 +01:00
MerryMage
396116ee61 A32: Add hook_hint_instructions option 2020-04-22 21:04:23 +01:00
MerryMage
2f2a859615 a32_jitstate: Consolidate upper bits of location descriptor into upper_location_descriptor 
Also solves a performance regression initially introduced by b6e8297e369f2dc4758bafe944e51efb8d1a2552,
primarily due to excessively mismatched load/store sizes causing less than optimal load-to-store forwarding.
 2020-04-22 21:04:23 +01:00
Merry
1c97edac77 Merge pull request #503 from lioncash/cmp 
A64: Implement half-precision variants of FCMEQ
 2020-04-22 21:04:22 +01:00
Merry
f252a62c1b Merge pull request #502 from lioncash/header 
General: Remove unnecessary includes
 2020-04-22 21:04:22 +01:00
Lioncash
11d1114a17 A64: Implement all half-precision variants of FCMEQ 2020-04-22 21:04:22 +01:00
Lioncash
349d4b577a General: Remove unnecessary includes 
Removes unnecessary header dependencies that have accumulated over time
as changes have been made. Lessens the amount of files that need to be
rebuilt when the headers change.
 2020-04-22 21:04:22 +01:00
Lioncash
43fd2b400a frontend/ir_emitter: Add half-precision opcode for FPVectorEquals 2020-04-22 21:04:22 +01:00
Lioncash
dd315e89eb A64/translate/*: Apply const where applicable 
Just some tidying up for consistency
 2020-04-22 21:04:22 +01:00
Lioncash
4f47861669 A64/translate/impl: Mark DecodeBitMasks and AdvSIMDExpandImm as static 
These don't rely on instance state to perform their behavior. They're
just helper functions.
 2020-04-22 21:04:22 +01:00
Lioncash
dddba94c17 disassembler_arm: Apply const where applicable 2020-04-22 21:04:22 +01:00
Lioncash
9365487797 frontend/A32/ir_emitter: Remove unnecessary includes 
std::initializer_list isn't used anywhere in here, and we can just
forward declare the CoprocReg enum to avoid needing to include the
header.
 2020-04-22 21:04:22 +01:00
Lioncash
bfa8035414 A32/A64: Make public header inclusions consistent 
For all public header inclusions, we use the <> form of including them
as opposed to "", which we typically use for internal headers.
 2020-04-22 21:04:22 +01:00
Lioncash
fb7d33830c A32: Make includes consistent 
Normalizes includes to be relative to the project root, like the rest of
the includes in the project.
 2020-04-22 21:04:22 +01:00
Lioncash
b57ed8917a frontend/A32/types: Remove redundant std::string initializer 
std::string initializes to empty by default. While we're at it, brace a
lone unbraced if statement.
 2020-04-22 21:04:22 +01:00
Lioncash
182ceb2807 General: Make parameter names from declarations and implementations consistent 
Most of the time when this occurs, it's a bug. Thankfully this isn't the
case. However, we can resolve these cases to make the codebase more
consistent.
 2020-04-22 21:04:22 +01:00
Lioncash
b301fcd520 A32/translate/translate: Add missing doxygen parameter string 2020-04-22 21:04:22 +01:00
Lioncash
6b9bf7868a General: Correct typos is code comments 2020-04-22 21:04:22 +01:00
MerryMage
7d20f3b861 A32/translate_thumb: Split off implementation into thumb16 and thumb32 2020-04-22 21:04:22 +01:00
Lioncash
b79ce71b0f ir/basic_block: std::move Terminal within SetTerminal and ReplaceTerminal 
A terminal isn't a trivial type (and boost::variant is allowed to heap
allocate), so we can std::move it here to avoid a redundant copy.
 2020-04-22 21:04:22 +01:00
MerryMage
e639aa1583 A32/translate: Rename translate_arm directory to impl 
Mirror what the A64 frontend does.
 2020-04-22 21:04:22 +01:00
Lioncash
63eff4e7cc ir/terminal: std::move constructor parameters where applicable 
Allows the compiler to choose the most suitable code in this scenario,
given a Terminal isn't a trivial type.
 2020-04-22 21:04:22 +01:00
MerryMage
5f8eb7c51c A32/location_descriptor: Add CPSR.IT to A32::LocationDescriptor 2020-04-22 21:04:22 +01:00
MerryMage
13f65f55eb PSR: Use Common::ModifyBit{,s} 2020-04-22 21:04:22 +01:00
MerryMage
74633301c1 A32: Add ITState 2020-04-22 21:04:22 +01:00
MerryMage
6e2cd35e4f a32_jitstate: Optimize runtime location descriptor calculation 
Calculation is now one unaligned 64-bit load.
 2020-04-22 21:04:22 +01:00
MerryMage
f178562ee7 a32_jitstate: Remove exception trap enables from FPSCR_MODE_MASK 
We don't currently use this for anything (we do not currently trap
floating point exceptions).

This frees these bits up for other purposes.
 2020-04-22 21:04:21 +01:00
Merry
fd6222f0a1 Merge pull request #500 from lioncash/cbz 
A32: Implement Thumb-1's CBZ/CBNZ instructions
 2020-04-22 21:04:21 +01:00
Merry
bab4e29075 Merge pull request #498 from lioncash/ahp 
A32/location_descriptor: Add AHP bit to the FPSCR mask
 2020-04-22 21:04:21 +01:00
Lioncash
87083af733 general: Remove trailing spaces 
General code-related cleanup. Gets rid of trailing spaces in the
codebase.
 2020-04-22 21:04:21 +01:00
Lioncash
03e6899fd7 A32: Implement Thumb-1's CBZ/CBNZ instructions 
Introduced in ARMv6T2, this allows for short forward branches.
 2020-04-22 21:02:47 +01:00
Lioncash
d02a4e6fc9 A32/location_descriptor: Add AHP bit to the FPSCR mask 
Ensures the alternate half-precision state is preserved within the
location descriptors, which will be necessary when implementing the
half-precision extensions for VFP and NEON.
 2020-04-22 21:02:47 +01:00
Merry
f4990a5f6b Merge pull request #499 from lioncash/movw 
A32: Implement ARM-mode MOVW
 2020-04-22 21:02:47 +01:00
Lioncash
bd755ae494 frontend/ir/ir_emitter: Add A32 equivalent to A64's SetCheckBit 
This will be used in a subsequent change to implement ARMv6T2's CBZ/CBNZ
Thumb-1 instructions.
 2020-04-22 21:02:47 +01:00
Lioncash
106c8c2473 A32: Implement ARM-mode MOVW 
Introduced to the ISA in ARMv6T2
 2020-04-22 21:02:47 +01:00
Lioncash
9935f3aa28 A32: Implement Thumb-1 variant of SEVL 
While we're at it, also add the Thumb-2 encoding to the encoding table
to make sure it isn't forgotten about in the future.
 2020-04-22 21:02:47 +01:00
Lioncash
9a097e307f A32: Implement the ARM-mode variant of SEVL 2020-04-22 21:02:47 +01:00
Lioncash
e89ca42048 A32: Implement Thumb-1 variant of YIELD 2020-04-22 21:02:47 +01:00
Lioncash
ebab7ede55 A32: Implement Thumb-1 variant of WFI 2020-04-22 21:02:47 +01:00
Lioncash
b4110af22a A32: Implement Thumb-1 variant of WFE 2020-04-22 21:02:47 +01:00
Lioncash
57675fe592 A32: Implement Thumb-1 variant of SEV 2020-04-22 21:02:47 +01:00
Lioncash
07699b47ba A32/translate_thumb: Add helper function for raising exceptions 
Similar to the variant within the ARM-mode translator visitor. This will
be used in subsequent changes to implement the hint instructions
introduced in ARMv7.
 2020-04-22 21:02:47 +01:00
Lioncash
f74762ae4e frontend/decoder/decoder_detail: Replace std::is_same, with std::is_same_v 
Same thing, same readability, less characters.
 2020-04-22 21:02:47 +01:00
Lioncash
64879396f6 A32: Implement Thumb-1 variant of NOP 2020-04-22 21:02:47 +01:00
Merry
6a67da1225 Merge pull request #493 from lioncash/ir 
frontend/ir/ir_emitter: Remove unnecessary logical shift overloads
 2020-04-22 21:02:47 +01:00
Merry
81b908b077 Merge pull request #495 from lioncash/bkpt 
A32: Implement Thumb-16's variant of BKPT
 2020-04-22 21:02:47 +01:00
Merry
30d28029a8 Merge pull request #492 from lioncash/vfp 
A32: Rename vfp2-related files to vfp
 2020-04-22 21:02:47 +01:00
Lioncash
b17a5d3365 A32: Implement Thumb-16's variant of BKPT 2020-04-22 21:02:47 +01:00
Lioncash
b902f72001 A32/disassembler_arm: Remove <unimplemented> from hint instruction output 
Given we now support hooking these hint instructions, we can consider
them implemented.
 2020-04-22 21:02:47 +01:00
Lioncash
0fa0bca22a A32: Handle different variants of PLD 2020-04-22 21:02:47 +01:00
Lioncash
c6f99235e1 frontend/ir/ir_emitter: Remove unnecessary logical shift overloads 
These aren't necessary anymore, now that the U32U64 overload already
exists.
 2020-04-22 21:02:46 +01:00
Merry
9ba503e394 Merge pull request #491 from lioncash/hint 
A32: Allow hooking of hint instructions in ARM mode.
 2020-04-22 21:02:46 +01:00
Lioncash
97277c598b A32: Rename vfp2-related files to vfp 
Now that we fuzz against Unicorn, we aren't just restricted to VFPv2.
VFPv3 and VFPv4 facilities can now be implemented. This renames
constructs mentioning VFPv2 to just refer to VFP.
 2020-04-22 21:02:46 +01:00
Lioncash
8c3122ff46 A64/translate/impl/impl: Mark locals const where applicable in DecodeBitMasks() 
Follows the convention of making immutable state explicit.
 2020-04-22 21:02:46 +01:00
Merry
a132b56d57 Merge pull request #490 from lioncash/crc32 
A32: Implement ARM-mode CRC32 instructions
 2020-04-22 21:02:46 +01:00
Lioncash
966e04d03d A32: Allow hooking of hint instructions in ARM mode. 
Mirrors the hooking functionality from the AArch64 frontend to make the
behavior of both consistent.
 2020-04-22 21:02:46 +01:00
Lioncash
134b586c5c frontend/ir/ir_emitter: Amend arguments to conversion opcodes 
Accidentally caused within 967d1fcc8d6f60749a162a96b997439450fed687.
That one's on me. My bad.
 2020-04-22 21:02:46 +01:00
Lioncash
e37689315d A32: Implement ARM-mode CRC32 instructions 
Implements the ARM-mode variants of the CRC32 instructions introduced
within ARMv8. This is also one of the instruction cases where there is
UNPREDICTABLE behavior that is constrained (we must do one of the
options indicated by the reference manual).

In both documented cases of constrained unpredictable behavior, we treat
the instructions as unpredictable in order to allow library users to
hook the unpredictable exception to provide the intended behavior they
desire.
 2020-04-22 21:02:46 +01:00
Lioncash
95d9baea67 {A32, A64}/types: Use std::array deduction guides where applicable 
We also make the arrays static here, as MSVC tends to load the whole
array every time the function is called, instead of storing the data
within rodata.

This also line breaks the elements a little earlier for readability.
 2020-04-22 21:02:46 +01:00
Lioncash
bac945f2d8 A32: Resolve parameter discrepancies discovered via use of the Imm template 2020-04-22 21:02:46 +01:00
Lioncash
e4c65721fe frontend/ir/type: Generify std::array declaration 
With deduction guides, we can eliminate the need to explicitly size the
array. Also newlines the elements based off their relation, making it
slightly nicer to read.
 2020-04-22 21:02:46 +01:00
Lioncash
4ba2318b2e A32: Replace immediate type aliases with the Imm template 
Replaces type aliases of raw integral types with the more type-safe Imm
template, like how the AArch64 frontend has been using it.

This makes the two frontends more consistent with one another.
 2020-04-22 21:02:46 +01:00
Lioncash
f96036b3f1 A32/barrier: Correct PC assignment within ISB 
The SetRegister() IR function doesn't allow specifying the PC as a
register. This is a discrepancy that slipped through (my bad). Instead,
we can use BranchWritePC(), like how the other similar PC modifying
locations do it.
 2020-04-22 21:02:46 +01:00
Lioncash
196e7b5e35 frontend/A32/ir_emitter: Mark locals as const where applicable 
Makes const usage consistent within the source file.
 2020-04-22 21:02:46 +01:00
Lioncash
511613c736 frontend/A32/types: Use helper function in operator+ overload 
Allows deduplicating an assert and a cast.
 2020-04-22 21:02:46 +01:00
Lioncash
8103652a91 frontend: Move imm.h to the top-level directory of the frontends 
Preparation to utilize the immediate type within the A32 backend as
well, which will allow eliminating numerous type aliases like Imm4,
Imm5, etc.
 2020-04-22 21:02:46 +01:00
Lioncash
796bb8a7f7 frontend/A64/types: Make RegNumber() and VecNumber() constexpr 
Given they simply perform casting, they can be safely made constexpr.
 2020-04-22 21:02:46 +01:00
Lioncash
64e51a6d4d A32/disassembler_arm: Mark utility functions as static where applicable 
These don't depend on class state and can be marked static to make that
explicit.
 2020-04-22 21:02:46 +01:00
Lioncash
0c43228ad5 frontend/A64/types: Use helper functions in operator+ overloads 
Allows us to get rid of another explicit cast.
 2020-04-22 21:02:46 +01:00
Lioncash
a1cace21a9 frontend/ir/ir_emitter: Apply const to locals where applicable 
Makes const usage consistent with all other functions in the source
file.
 2020-04-22 21:02:46 +01:00
Lioncash
0a35836998 frontend/ir/ir_emitter: Use switch constructs in floating point opcodes where applicable 
This'll reduce the amount of noise necessary in changes implementing
half-precision instructions, as the type can just be prepended to the
switch cases, instead of rewriting the whole if/else branch.
 2020-04-22 21:02:46 +01:00
Lioncash
8316d231e9 A32: Implement barrier instructions introduced in ARMv7 
Provides basic implementations of the barrier instruction introduced
within ARMv7. Currently these simply mirror the behavior of the AArch64
equivalents.
 2020-04-22 21:02:46 +01:00
Lioncash
7fc3bd689d A32: Implement ARM-mode MLS 2020-04-22 21:02:46 +01:00
Lioncash
8b338b7def A32: Implement ARM-mode MOVT 2020-04-22 21:02:46 +01:00
Lioncash
877fa0f8c3 A32: Implement ARM-mode SBFX 2020-04-22 21:02:46 +01:00
Lioncash
47218ee65d A32: Implement ARM-mode UBFX 2020-04-22 21:02:46 +01:00
Lioncash
2970b34e3c A32: Implement ARM-mode BFI 2020-04-22 21:02:46 +01:00
Lioncash
fab3a59e05 A32: Implement ARM-mode BFC 2020-04-22 21:02:46 +01:00
Lioncash
7305d13221 A32: Implement ARM-mode RBIT 2020-04-22 21:02:46 +01:00
Lioncash
b2f7a0e7ba A32: Implement ARM-mode SDIV/UDIV 
Now that we have Unicorn in place, we can freely implement instructions
introduced in newer versions of the ARM architecture.
 2020-04-22 21:02:46 +01:00
Lioncash
c0ae23bbb7 A32/translate_thumb: Clean up formatting 
Performs a similar tidying up of the Thumb translator, like what was
done with the regular ARM translator to make it consistent with the rest
of the codebase.

The A32 backend (both Thumb and ARM), will likely see more changes to it
in the near future, so this just acts as a "dusting off".
 2020-04-22 21:02:46 +01:00
Merry
837c23a8ec Merge pull request #483 from lioncash/invert 
frontend/ir/cond: Remove unused invert() function
 2020-04-22 21:02:46 +01:00
Merry
09ee64ea98 Merge pull request #482 from lioncash/fixedfp 
A64: Handle half-precision variants of FP->Fixed instructions
 2020-04-22 21:02:45 +01:00
Lioncash
06ec6ab0da frontend/ir/cond: Remove unused invert() function 
This is no longer used by anything in the codebase, so it can be
removed.
 2020-04-22 21:01:46 +01:00
Lioncash
64e3d233f4 A64: Handle half-precision variants of FP->Fixed-point instructions 2020-04-22 21:01:45 +01:00
Lioncash
4fc531f71b ir/basic_block: Forward declare headers where applicable 
Now that the constructor and destructors have been placed within the cpp
file, we can forward declare the memory pool data structures. Now, a
change to the memory pool code won't ripple across the entirety of the
IR emitter.
 2020-04-22 21:01:45 +01:00
Lioncash
427b7afd66 frontend/ir/microinstruction: Add missing fixed-point opcodes to ReadsFromAndWritesToFPSRCumulativeExceptionBits() 2020-04-22 21:01:45 +01:00
Lioncash
9309d95b17 ir/block: Default ctor and dtor in the cpp file 
Prevents potentially inlining allocation code everywhere. While we're at
it, also explicitly delete/default the copy/move constructor/assignment
operators to be explicit about them.
 2020-04-22 21:01:45 +01:00
Lioncash
604f39f00a frontend/ir_emitter: Add half-precision->fixed-point opcodes 2020-04-22 21:01:45 +01:00
Lioncash
471eb77bc9 A64: Implement FRSQRTS' half-precision vector variant 2020-04-22 21:01:45 +01:00
Lioncash
f9b2862217 A64: Implement FRSQRTS' half-precision scalar variant 
With the necessary machinery in place, we can now handle the
half-precision variant.
 2020-04-22 21:01:45 +01:00
Lioncash
96356fac93 frontend/ir_emitter: Add half-precision opcode variant of FPVectorRSqrtStepFused 2020-04-22 21:01:45 +01:00
Merry
45864133f5 Merge pull request #478 from lioncash/stepfused 
A64: Handle half-precision variants of FRECPE and FRECPS
 2020-04-22 21:01:44 +01:00
Lioncash
824c551ba2 frontend/ir_emitter: Add half-precision opcode variant of FPRSqrtStepFused 2020-04-22 21:01:44 +01:00
Lioncash
3739d92097 A64: Implement half-precision vector variant of FRECPE 2020-04-22 21:01:44 +01:00
Lioncash
7b212ec8ae A64: Implement half-precision variant of FRSQRTE's vector variant 2020-04-22 21:01:44 +01:00
Lioncash
0945a491bd A64: Implement half-precision scalar variant of FRECPE 2020-04-22 21:01:44 +01:00
Lioncash
77c84bcf9b A64: Implement half-precision variant of FRSQRTE's scalar variant 2020-04-22 21:01:44 +01:00
Lioncash
86b7626a2f A64: Implement half-precision vector variant of FRECPS 2020-04-22 21:01:44 +01:00
Lioncash
037acb17b9 frontend/ir_emitter: Add half-precision opcode variant for FPVectorRSqrtEstimate 2020-04-22 21:01:44 +01:00
Lioncash
de43f011a7 A64: Implement half-precision scalar variant of FRECPS 2020-04-22 21:01:44 +01:00
Lioncash
5dba99b4f4 frontend/ir_emitter: Add half-precision opcode variant for FPRSqrtEstimate 2020-04-22 21:01:44 +01:00
Lioncash
825a3ea16f frontend/ir_emitter: Add half-precision opcode for FPVectorRecipEstimate 2020-04-22 21:01:44 +01:00
Lioncash
2184d24e8f frontend/ir_emitter: Add half-precision opcode for FPRecipEstimate 2020-04-22 21:01:44 +01:00
Lioncash
d7f394fc1a A64: Enable half-precision vector FRINT* variants 2020-04-22 21:01:44 +01:00
Lioncash
5d5c9f149f frontend/ir_emitter: Add half-precision opcode for FPVectorRecipStepFused 2020-04-22 21:01:44 +01:00
Lioncash
24f583c498 A64: Enable half-precision variants of floating-point FRINT* variants 
With all the backing machinery in place, we can remove the fallback
check for half-precision.
 2020-04-22 21:01:44 +01:00
Lioncash
6da0411111 frontend/ir_emitter: Add half-precision opcode for FPRecipStepFused 2020-04-22 21:01:44 +01:00
Lioncash
fb829b9525 frontend/microinstruction: Add FPVectorRoundInt types to ReadsFromAndWritesToFPSRCumulativeExceptionBits() 
All variants were previously missing from this.
 2020-04-22 21:01:44 +01:00
Lioncash
5b4673da4b frontend/ir_emitter: Add half-precision variant of FPVectorRoundInt 2020-04-22 21:01:44 +01:00
Lioncash
ad0c698f89 frontend/ir_emitter: Add half-precision variant of FPRoundInt 2020-04-22 21:01:44 +01:00
Merry
cb9a1b18b6 Merge pull request #475 from lioncash/muladd 
A64: Enable half-precision variants of floating-point multiply-add instructions
 2020-04-22 21:01:44 +01:00
Merry
d6db7ad46c Merge pull request #474 from lioncash/bracing 
load_store_*: Make bracing consistent and variables const where applicable
 2020-04-22 21:01:44 +01:00
Merry
1b6520f5dd A64/location_descriptor: Ensure FZ16 is included in the FPCR mask 2020-04-22 21:01:44 +01:00
Merry
13f421c27d Merge pull request #473 from lioncash/sqshlu 
A64: Implement SQSHLU
 2020-04-22 21:01:44 +01:00
Lioncash
b5bf890584 load_store_*: Make bracing consistent and variables const where applicable 
Makes bracing consistent, and variables const where applicable to be
consistent with the rest of the codebase.

In most bracing cases, they'd need to be added to conditionals that
would involve checking stack pointer alignment in the future anyways.
 2020-04-22 21:01:44 +01:00
Lioncash
9a58c3f1c7 A64: Implement FMLA/FMLS' half-precision vector indexed variants 2020-04-22 21:01:44 +01:00
Merry
d7da53a74b Merge pull request #472 from lioncash/exception 
general: Mark hash functions as noexcept
 2020-04-22 21:01:44 +01:00
Lioncash
9dcc04e106 A64: Implement SQSHLU's scalar variant 2020-04-22 21:01:44 +01:00
Merry
b91c6c8bae Merge pull request #471 from lioncash/sqrdmulh 
A64: Implement SQRDMULH's scalar vector variant
 2020-04-22 21:01:44 +01:00
Lioncash
1fdd3ef8a0 A64: Implement FMLA/FMLS' half-precision scalar indexed variants 2020-04-22 21:01:44 +01:00
Lioncash
2d59d10ac8 A64: Implement SQSHLU's vector variant 
The vector shift by immediate category is now fully implemented.
 2020-04-22 21:01:44 +01:00
Merry
b5e25959d9 Merge pull request #470 from lioncash/assert 
general: Replace unreachable-imitating assertions with UNREACHABLE()
 2020-04-22 21:01:44 +01:00
Lioncash
d6606deda2 A64: Implement half-precision vector variants of FMLA/FMLS 2020-04-22 21:01:44 +01:00
Lioncash
a4cadf1cd9 frontend/ir_emitter: Add opcodes for signed saturated left shifts with unsigned saturation 2020-04-22 21:01:44 +01:00
Lioncash
ec6b3ae084 ir/frontend: Add half-precision opcode for FPVectorMulAdd 2020-04-22 21:01:44 +01:00
Lioncash
5f74d25bf7 A64: Enable half-precision floating point variants of FP data-processing three register instructions 
This handles half-precision floating point for:

- FMADD
- FMSUB
- FNMADD
- FNMSUB
 2020-04-22 21:01:44 +01:00
Lioncash
bd82513199 frontend/ir_emitter: Add half-precision opcode for FPMulAdd 2020-04-22 21:01:44 +01:00
Lioncash
7bb5440507 general: Mark hash functions as noexcept 
Generally hash functions shouldn't throw exceptions. It's also a
requirement for the standard library-provided hash functions to not
throw exceptions.

An exception to this rule is made for user-defined specializations,
however we can just be consistent with the standard library on this to
allow it to play nicer with it.

While we're at it, we can also make the std::less specializations
noexcpet as well, since they also can't throw.
 2020-04-22 21:01:43 +01:00
Lioncash
3b46b4a37d A64: Implement SQRDMULH's scalar vector variant 
Implements the scalar variant in terms of the vector variant for the
time being.
 2020-04-22 21:01:43 +01:00
Lioncash
fe95575b95 general: Replace unreachable-imitating assertions with UNREACHABLE() 
We can just use the self-documenting assertion for indicating
unreachable paths, instead of manually passing false and providing a
message.
 2020-04-22 21:01:43 +01:00
Lioncash
64de80839e A64/impl: Reorganize peculiar void use in V_scalar 
To a reader this might look particularly strange, given the function
itself has a void return value, but this is actually valid, given the
function in the return statement also has a void return value.

This instead alters it to be a little easier to parse and potentially be
a little less confusing at a glance.
 2020-04-22 21:01:43 +01:00
Merry
9a4e3b24e4 Merge pull request #467 from lioncash/reserved 
A64: Handle reserved instruction cases more specifically where applicable
 2020-04-22 21:01:43 +01:00
Lioncash
8309d49588 A64: Handle reserved instruction cases more specifically where applicable 
These are cases that are defined as reserved within the ARMv8 reference
manual, so we can handle them as such instead of as unallocated
encodings.

While this doesn't actually change emulated behavior, it does at least
allow the JIT to generate the more appropriate exception.
 2020-04-22 21:00:47 +01:00
Lioncash
6c2c68bce6 A64: Implement FCMLA's indexed element variant 
With this, all of the instructions introduced with ARMv8.3-CompNum have
an implementation.
 2020-04-22 21:00:47 +01:00
Lioncash
7bc7042104 simd_scalar_shift_by_immediate: Change UnallocatedEncoding() path in SaturatingShiftLeft to ReservedValue() 
Strictly speaking, immh being zero is defined as reserved in the ARMv8
reference manual. This was just an error on my part when introducing the
SQSHL immediate scalar variant.
 2020-04-22 21:00:47 +01:00
Lioncash
b1b4487e4d A64: Implement UQSHL (immediate)'s scalar variant 
Like SQSHL's immediate scalar variant, we can also implement UQSHL's
immediate scalar variant in terms of the vector variant for the time
being.
 2020-04-22 21:00:47 +01:00
Lioncash
e1b4ff1068 simd_scalar_shift_by_immediate: Migrate SQSHL implementation to file-scope function 
This will allow it to be reused for the implementation of UQSHL.
 2020-04-22 21:00:47 +01:00
Lioncash
3649dc6d9a A64: Implement scalar variant of SQSHL (immediate) 
This can be handled in terms of the vector variant for the time being.
 2020-04-22 21:00:47 +01:00
Merry
01bb1cdd88 Merge pull request #458 from lioncash/float-op 
A64: Handle half-precision floating point in FABS, FNEG, and scalar FMOV
 2020-04-22 20:58:12 +01:00
Lioncash
28a8b4d210 A64: Handle half-precision floating point in scalar FMOV 
This is simply performing a scalar value transfer between registers
without conversions, so this is trivial to handle as-is.
 2020-04-22 20:58:12 +01:00
Lioncash
d7ac5a664f A64: Handle half-precision floating point in FCVTL 
Like FCVTN, now that we have half-precision floating point conversion
functions available, we can go ahead and use those to eliminate the
interpreter fallback.
 2020-04-22 20:58:12 +01:00
Lioncash
fe84ecb780 A64: Handle half-precision floating point in scalar FABS 
Now that we have the half-precision variant of the opcode added, we can
simply handle the instruction instead of treating it as undefined.
 2020-04-22 20:58:12 +01:00
Lioncash
fac9224d5e A64: Handle half-precision floating point in FCVTN 
Now that we have IR instructions for performing conversions with
half-precision floating point, we can also handle half-precision values
within FCVTN.
 2020-04-22 20:58:12 +01:00
Lioncash
8309ec7a9f frontend/ir_emitter: Add half-precision variant of FPAbs 2020-04-22 20:58:12 +01:00
Lioncash
16de99d3e3 A64: Enable FCVT floating-point conversions for half-precision 
With this, we no longer have to fall back to the interpreter in any of
the FCVT floating-point conversion instructions.
 2020-04-22 20:58:12 +01:00
Lioncash
10abc77fad A64: Handle half-precision floating point in scalar FNEG 
With the half-precision variant of the FPNeg opcode added, we can
utilize it here to emulate the half-precision variant of FNEG.
 2020-04-22 20:58:12 +01:00
Lioncash
e4c259d69f frontend/ir_emitter: Add half->{single, double} and {double, single}->half conversion opcodes 2020-04-22 20:58:12 +01:00
Lioncash
c97efcb978 frontend/ir_emitter: Add half-precision variant of FPNeg 2020-04-22 20:58:12 +01:00
Merry
f01afc5ae6 Merge pull request #456 from lioncash/mov 
A64: Enable FMOV (general) for half-precision floating point
 2020-04-22 20:58:12 +01:00
Merry
c1ce94872d Merge pull request #455 from lioncash/sqrdmulh-scalar 
A64: Implement SQRDMULH and SQDMULL's scalar indexed variants
 2020-04-22 20:58:11 +01:00
Lioncash
25a7256ee1 A64: Enable FMOV (general) for half-precision floating point 
This just transfers values between vector registers and general-purpose
registers with no conversions performed, so this is trivial to add
support for half-precision to.
 2020-04-22 20:58:11 +01:00
Lioncash
97dd3d0596 A64: Implement SQRDMULH's scalar indexed element variant 2020-04-22 20:58:11 +01:00
Lioncash
49b51e34f1 simd_vector_x_indexed_element: Deduplicate index and Vm operand construction 2020-04-22 20:58:11 +01:00
Lioncash
692aba91b6 A64: Implement SQDMULL{2}'s scalar indexed element variant 2020-04-22 20:58:11 +01:00
Lioncash
c043b831d5 A64: Implement SQDMULL{2}'s by-element variant 2020-04-22 20:58:11 +01:00
Lioncash
72af5a3dff simd_scalar_x_indexed_element: Factor out index and Vm argument construction 
This will be useful in the implementations of SQRDMULH and SQDMULL{2} as
well.
 2020-04-22 20:58:11 +01:00
Lioncash
224ff0afaa A64: Implement SQRDMULH's by-index vector variant 2020-04-22 20:58:11 +01:00
Lioncash
3a3542414b A64: Implement FRECPX's half-precision floating point variant 2020-04-22 20:58:11 +01:00
Lioncash
bd892ec4ef frontend/ir/ir_emitter: Amend FPRecipExponent to handle half-precision floating point 2020-04-22 20:58:11 +01:00
Lioncash
974fbf0677 frontend/ir/value: Add U16U32U64 type to represent floating point types 2020-04-22 20:58:11 +01:00
Lioncash
126c29a9e9 A64: Implement SQSHRN, SQSHRUN, and UQSHRN's scalar variants 
These can just be implemented in terms of the vector variants for the
time being.
 2020-04-22 20:58:11 +01:00
Lioncash
dd7433f9d3 A64: Amend prototypes of some SIMD scalar shift by immediate opcodes 
These take a vector for a destination.
 2020-04-22 20:58:11 +01:00
Merry
bbd5330ad2 Merge pull request #447 from lioncash/flag 
A64: Implement CFINV, RMIF, AXFlag and XAFlag
 2020-04-22 20:58:11 +01:00
Merry
fb039e232c Merge pull request #442 from lioncash/fcvtxn 
A64: Implement scalar and vector variants of FCVTXN
 2020-04-22 20:58:11 +01:00
Merry
4f937c1ee1 Merge pull request #446 from lioncash/sqshl 
A64: Implement scalar variants of SQSHL (register) and UQSHL (register)
 2020-04-22 20:58:11 +01:00
Lioncash
aa22db534b A64: Implement AXFlag and XAFlag 2020-04-22 20:58:11 +01:00
Merry
d74cccbc84 Merge pull request #445 from lioncash/sqrt 
A64: Implement single and double-precision vector variant of FSQRT
 2020-04-22 20:58:11 +01:00
Lioncash
20ffe568d0 A64: Implement RMIF 2020-04-22 20:58:11 +01:00
Merry
6d7e7c3269 Merge pull request #443 from lioncash/flag 
A64: Rearrange flag format/manipulation instructions
 2020-04-22 20:58:11 +01:00
Lioncash
51b526e453 A64: Implement CFINV 2020-04-22 20:58:11 +01:00
Lioncash
597a8be5d5 ir: Add A64-specific opcodes for getting and setting raw NZCV values 
This will be necessary to implement the flag manipulation and flag
format instructions.
 2020-04-22 20:58:11 +01:00
Lioncash
d3515279df A64: Implement the vector version of FCVTXN 2020-04-22 20:58:10 +01:00
Lioncash
17aea0b997 A64: Implement UQSHL (register)'s scalar variant 
This can be implemented in terms of the vector variant.
 2020-04-22 20:58:10 +01:00
Lioncash
c99d4b762e A64: Implement single and double-precision vector variant of FSQRT 2020-04-22 20:58:10 +01:00
Lioncash
54e0b487f3 A64: Rearrange flag format/manipulation instructions 
Gives these instructions better categorical labeling.
 2020-04-22 20:58:10 +01:00
Lioncash
302f56b36a A64: Fall back to interpreting for FCADD and FCMLA half-precision variants 
Rather than straight-up treating them as undefined, we can fall back to an
interpreter in this case.
 2020-04-22 20:58:10 +01:00
Lioncash
4339a8fff6 A64: Implement the scalar version of FCVTXN 2020-04-22 20:58:10 +01:00
Lioncash
35ddf68ad5 A64: Implement SQSHL (register)'s scalar variant 
We can implement this in terms of the vector variant.
 2020-04-22 20:58:10 +01:00
Lioncash
5cf1478620 frontend/ir: Add opcodes for vector square roots 2020-04-22 20:58:10 +01:00
Lioncash
36027ebef5 frontend/ir/microinstruction: Add missing cases for FPRecipExponent{32,64} for ReadsFromAndWritesToFPSRCumulativeExceptionBits() 
This was intended to be added within #437, but was missed
 2020-04-22 20:58:10 +01:00
Lioncash
7c81a58ed3 frontend/ir/ir_emitter: Alter parameters of FPDoubleToSingle() and FPSingleToDouble() to pass along desired rounding mode 
This will be necessary to special-case the non-IEEE Von Neumann rounding
to odd rounding mode.
 2020-04-22 20:58:10 +01:00
Merry
40b081438a Merge pull request #439 from lioncash/fcmla 
A64: Implement FCADD and FCMLA
 2020-04-22 20:58:10 +01:00
Merry
d91192681a Merge pull request #438 from lioncash/fmulx 
A64: Implement scalar double/single precision FMULX (by element)
 2020-04-22 20:58:10 +01:00
Lioncash
ed29ef8cca A64: Implement FCMLA 2020-04-22 20:58:10 +01:00
Merry
9f11720a69 Merge pull request #437 from lioncash/frecpx 
A64: Implement FRECPX (single, double precision)
 2020-04-22 20:58:10 +01:00
Lioncash
bdcea0b0dc A64: Implement scalar double/single precision FMULX (by element) 2020-04-22 20:58:10 +01:00
Lioncash
5ce17574f9 A64: Implement FCADD 2020-04-22 20:58:10 +01:00
Merry
34d917f34e Merge pull request #436 from lioncash/no-alloc 
A64: Implement LDNP/STNP
 2020-04-22 20:58:10 +01:00
Lioncash
e44730ba6d A64: Implement FRECPX (single, double precision) 2020-04-22 20:58:10 +01:00
Lioncash
bfaeb08d3c A64: Implement LDNP/STNP 
LDNP and STNP indicate that a memory access is non-temporal/streaming
(i.e. unlikely to be repeated), allowing data caching to not be
performed. However, given this is only a hint, we can treat these two
instructions as regular LDP and STP instructions for the time being.
 2020-04-22 20:58:10 +01:00
Lioncash
9cf3c25811 frontend/ir/ir_emitter: Add opcodes for floating point reciprocal exponents 2020-04-22 20:58:10 +01:00
Lioncash
05a6ab691d translate_arm/coprocessor: Minor tidying up 2020-04-22 20:58:10 +01:00
Lioncash
1e32a09c03 translate_arm/vfp2: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
e209b31073 translate_arm/synchronization: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
9514e3602e translate_arm/status_register_access: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
c6aa1a708a translate_arm/saturated: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
a72813599a translate_arm/reversal: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
7be56e6b67 translate_arm/parallel: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
3c00a616d6 translate_arm/packing: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
c711188f46 translate_arm/multiply: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
c8dad40d81 translate_arm/misc: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
a7bf5ff77d translate_arm/load_store: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
f4b19a7393 translate_arm/extension: Invert conditionals where applicable 2020-04-22 20:58:09 +01:00
Lioncash
c2de6ecfd0 translate_arm/exception_generating: Invert conditionals where applicable 2020-04-22 20:58:09 +01:00
Lioncash
d8a8d3b073 translate_arm/data_processing: Invert conditionals where applicable 2020-04-22 20:58:09 +01:00
Lioncash
df5c51ff47 translate_arm/branch: Invert conditionals where applicable 
Allows unindenting code a bit.
 2020-04-22 20:58:09 +01:00
Lioncash
ee973f13c7 frontend/A32/ir_emitter: Mark PC() and AlignPC() as const-qualified member functions 
These don't modify instance state, so they can be const-qualified member
functions.
 2020-04-22 20:57:38 +01:00
Lioncash
3a2dd09122 frontend/A64/ir_emitter: Mark PC() and AlignPC() as const qualified member functions 
These don't actually alter any instance state.
 2020-04-22 20:57:38 +01:00
MerryMage
e3898e628e A64: Implement FMULX (by element), single and double precision variants 2020-04-22 20:57:37 +01:00