2037 commits

Author	SHA1	Message	Date
MerryMage	cbc9f361b0	IR: Implement VectorSub	2020-04-22 20:46:13 +01:00
MerryMage	3f93c77ace	A64: Implement SIMD instruction USRA, vector variant	2020-04-22 20:46:13 +01:00
MerryMage	fb9d20f27f	A64: Implement SIMD instruction USHR, vector variant	2020-04-22 20:46:13 +01:00
MerryMage	b22c5961f9	IR: Implement VectorLogicalShiftRight	2020-04-22 20:46:13 +01:00
MerryMage	7ff280827b	A64: Implement SIMD instructions USHLL, USHLL2	2020-04-22 20:46:13 +01:00
MerryMage	59ace60b03	IR: Implement VectorZeroExtend	2020-04-22 20:46:13 +01:00
MerryMage	d3a4e1efe2	IR: Vector instructions now take esize argument in emitter	2020-04-22 20:46:13 +01:00
MerryMage	1d0cd95b23	A64: Implement SIMD instruction SHL	2020-04-22 20:46:13 +01:00
MerryMage	f6247125c0	IR: Implement VectorLogicalShiftLeft{8,16,32,64}	2020-04-22 20:46:13 +01:00
MerryMage	15e8231f24	opcodes: Sort vector IR opcodes alphabetically	2020-04-22 20:46:13 +01:00
MerryMage	d74f4e35f6	block_of_code: Increase constant pool size	2020-04-22 20:46:13 +01:00
MerryMage	e69288f803	devirtualize: MinGW uses Intanium MFP ABI	2020-04-22 20:46:13 +01:00
MerryMage	ad428cbd7a	callback: Properly handle calls with return pointers and simplify interface	2020-04-22 20:46:13 +01:00
FernandoS27	15871910af	Implemented BSL, BIC, BIT and BIF vector instructions	2020-04-22 20:46:13 +01:00
MerryMage	7a87e3fc55	devirtualize: Handle Windows ABI	2020-04-22 20:46:13 +01:00
MerryMage	ba4a779c62	A32/decoder/arm: bug: Correct bitstring for SRS	2020-04-22 20:46:13 +01:00
MerryMage	f808a0fbde	devirtualize: Devirtualize Itanium ABI MFPs at runtime	2020-04-22 20:46:13 +01:00
MerryMage	afe16fa0f3	cast_util: Add BitCast and BitCastPointee	2020-04-22 20:46:13 +01:00
Lioncash	4e33629b0e	A64: Move SDIV and UDIV out of data_processing_multiply.cpp	2020-04-22 20:46:13 +01:00
Lioncash	35a29a9665	A64: Implement ZIP1	2020-04-22 20:46:13 +01:00
FernandoS27	586854117b	Implemented UMULH and SMULH instructions	2020-04-22 20:46:13 +01:00
MerryMage	1a7b7b541a	A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate) ... There wasn't a clean way to seperate these instructions out.	2020-04-22 20:46:13 +01:00
MerryMage	8ab7d8175c	impl: Add AdvSIMDExpandImm	2020-04-22 20:46:13 +01:00
MerryMage	ea69cb4474	A64: Implement SUB (vector), scalar variant	2020-04-22 20:46:13 +01:00
MerryMage	4c5871d5d5	A64: Implement ADD (vector), scalar variant	2020-04-22 20:46:13 +01:00
MerryMage	2a0850c068	A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)	2020-04-22 20:46:13 +01:00
MerryMage	7b33772ac6	A64: Implement BIC (vector, register)	2020-04-22 20:46:13 +01:00
MerryMage	eb5591859c	A64: Implement FMOV (general)	2020-04-22 20:46:13 +01:00
MerryMage	dd88cee15a	translate/impl: Add Vpart	2020-04-22 20:46:13 +01:00
MerryMage	cc9efd13c9	A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR	2020-04-22 20:46:13 +01:00
MerryMage	81713c2b77	A64: Implement FCCMPE	2020-04-22 20:46:13 +01:00
MerryMage	ef906dbbfa	A64: Implement FCCMP	2020-04-22 20:46:13 +01:00
MerryMage	44c3c2312a	a64_jitstate: Remove unnecessary FPSCR_nzcv member	2020-04-22 20:46:13 +01:00
MerryMage	aac5af50e2	IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them	2020-04-22 20:46:13 +01:00
Lioncash	2ee39d6b36	A64: Implement FMOV (register)	2020-04-22 20:46:13 +01:00
MerryMage	b02b861242	A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR	2020-04-22 20:46:13 +01:00
Lioncash	5a65313236	A64: Implement CCMP (immediate)	2020-04-22 20:46:13 +01:00
Lioncash	ab4664de61	A64: Implement CCMN (immediate)	2020-04-22 20:46:13 +01:00
Lioncash	a6c6539109	A64: Implement CCMP (register)	2020-04-22 20:46:13 +01:00
Lioncash	22632db337	microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement	2020-04-22 20:46:13 +01:00
MerryMage	c5033b5dda	A64: Implement CCMN (register)	2020-04-22 20:46:13 +01:00
MerryMage	dd2a6684fe	IR: Add ConditionalSelectNZCV instruction	2020-04-22 20:46:13 +01:00
MerryMage	4491746eae	A64: Implement FNEG	2020-04-22 20:46:13 +01:00
MerryMage	db958061a3	A64: Implement FABS	2020-04-22 20:46:13 +01:00
MerryMage	8765b421b7	A64: Implement FCSEL	2020-04-22 20:46:13 +01:00
MerryMage	7e82d8eede	A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)	2020-04-22 20:46:13 +01:00
MerryMage	2409e5d082	A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)	2020-04-22 20:46:13 +01:00
MerryMage	b173fcf34e	backend_x64: Simplify FPDoubleToU32 and FPSingleToU32 ... They're inaccurate in terms of FPSR at the moment anyway.	2020-04-22 20:46:13 +01:00
MerryMage	56bc7825ef	A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)	2020-04-22 20:46:13 +01:00
Lioncash	d040920727	Common: Put AES code within its own nested namespace ... Prevents the functions from potentially clashing with other stuff in Common in the future	2020-04-22 20:46:13 +01:00
Lioncash	40614202e7	A64: Implement AESD	2020-04-22 20:46:13 +01:00
Lioncash	ccef85dbb7	A64: Implement AESE	2020-04-22 20:46:13 +01:00
MerryMage	68f46c8334	backend_x64: Use a reference to BlockOfCode instead of a pointer	2020-04-22 20:46:13 +01:00
MerryMage	8931ee346b	IR: Add IR instruction NZCVFromPackedFlags ... This instruction expects NZCV to be in the high bits. i.e.: The positions they were in PSTATE.	2020-04-22 20:46:13 +01:00
MerryMage	0bb4474fb9	A64: Implement INS (general)	2020-04-22 20:46:13 +01:00
MerryMage	d13704fdef	A64: Implement INS (element)	2020-04-22 20:46:13 +01:00
MerryMage	0642d49919	A64: Implement SMOV	2020-04-22 20:46:13 +01:00
MerryMage	5297027ebe	A64: Implement UMOV	2020-04-22 20:46:13 +01:00
MerryMage	47661b746b	basic_block: Fix bogus GCC maybe-uninitialized warning	2020-04-22 20:46:13 +01:00
MerryMage	1fb0957aa3	A64: Implement FCVT	2020-04-22 20:46:13 +01:00
MerryMage	ca38225e08	fuzz_with_unicorn: Skip instructions that need to be interpreted	2020-04-22 20:46:13 +01:00
MerryMage	4be55b8b84	A64: Implement FMOV (scalar, immediate)	2020-04-22 20:46:13 +01:00
MerryMage	a07c05ea51	A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)	2020-04-22 20:46:13 +01:00
MerryMage	93fcbdf1e2	A64: Implement FCMP, FCMPE	2020-04-22 20:46:13 +01:00
MerryMage	75b8a76630	a64_jitstate: A64 does not have a seperate FPSCR.NZCV	2020-04-22 20:46:13 +01:00
MerryMage	99d8ebe4d5	A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)	2020-04-22 20:46:13 +01:00
MerryMage	429dc24587	IR: Merge U32 and U64 variants of FP instructions	2020-04-22 20:46:13 +01:00
MerryMage	ed2bedec43	A64: Implement {ST,LD}{1,2,3,4} (multiple structures)	2020-04-22 20:46:13 +01:00
MerryMage	6414736a8d	emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1 ... This bug wasn't discovered earlier because we previously only used index == 0.	2020-04-22 20:46:13 +01:00
MerryMage	ebfc51c609	IR: Implement VectorSetElement{8,16,32,64}	2020-04-22 20:46:13 +01:00
Lioncash	a5c4fbc783	A64: Implement AESIMC and AESMC	2020-04-22 20:46:13 +01:00
Lioncash	744495e23d	iterator_util: Make Reverse constexpr ... C++17 makes non-member rbegin(), rend(), crbegin(), and crend() constexpr, allowing this to also be constexpr.	2020-04-22 20:46:12 +01:00
Lioncash	ab9b5fb8aa	Common: Relocate common bits of CRC32 ... Allows the algorithm to be used in any other potential backend.	2020-04-22 20:46:12 +01:00
Lioncash	af1384d700	A64: Implement CRC32	2020-04-22 20:46:12 +01:00
MerryMage	64761dbc72	scope_exit: Add SCOPE_SUCCESS and SCOPE_EXIT	2020-04-22 20:46:12 +01:00
MerryMage	bafb39ebc5	A64: Add Disassemble method	2020-04-22 20:46:12 +01:00
MerryMage	cc0eb18a0b	A32: data_processing: Remove !S assertions	2020-04-22 20:46:12 +01:00
MerryMage	865a30eb0d	A32: Implement BKPT	2020-04-22 20:46:12 +01:00
MerryMage	f023bbb893	A32: Add ExceptionRaised IR instruction and use it	2020-04-22 20:46:12 +01:00
Lioncash	7ffbebf290	A64: Implement CRC32C	2020-04-22 20:46:12 +01:00
MerryMage	d7044bc751	assert: Use fmt in ASSERT_MSG	2020-04-22 20:46:12 +01:00
MerryMage	52268298a8	a64_emit_x64: Perform RSB predictions	2020-04-22 20:46:12 +01:00
MerryMage	98ec9c5f90	A32: Change UserCallbacks to be similar to A64's interface	2020-04-22 20:46:12 +01:00
Lioncash	b9ce660113	reg_alloc: std::move RegAlloc's function argument	2020-04-22 20:46:12 +01:00
Lioncash	ed561d6653	General: Add missing override specifiers	2020-04-22 20:46:12 +01:00
MerryMage	b2d99eddc6	EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128	2020-04-22 20:46:12 +01:00
MerryMage	f4f774f9f6	a64_get_set_elimination_pass: Simplify algorithm	2020-04-22 20:46:12 +01:00
MerryMage	54de64f5bf	a64_emit_x64: bug: x64 sign-extends 32-bit immediates	2020-04-22 20:46:12 +01:00
MerryMage	6fc228f7fd	ir_opt: Add A64 Get/Set Elimination Pass	2020-04-22 20:46:12 +01:00
MerryMage	e01b500aea	ir_emitter: Allow the insertion point for new instructions to be set	2020-04-22 20:46:12 +01:00
MerryMage	af793c2527	{a32,a64}_interface: Predict entrypoint	2020-04-22 20:46:12 +01:00
Lioncash	7734cf1050	A64: Implement EXTR	2020-04-22 20:46:12 +01:00
MerryMage	88ae7fce52	A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)	2020-04-22 20:44:38 +01:00
MerryMage	d497464c9f	a64_jitstate: Have 128-bit wide spills	2020-04-22 20:44:38 +01:00
MerryMage	b513b2ef05	IR: Implement IR instructions A64{Get,Set}S	2020-04-22 20:44:38 +01:00
MerryMage	16fa2cd8f6	a64_emit_x64: Use xword from Xbyak::util	2020-04-22 20:44:38 +01:00
Lioncash	67443efb62	General: Convert multiple namespace specifiers to nested namespace specifiers where applicable ... Makes namespacing a little less noisy	2020-04-22 20:44:38 +01:00
Lioncash	7abd673a49	A64: Zero upper 64 bits in ORN if using the 64-bit variant ... Resolves a TODO	2020-04-22 20:44:38 +01:00
MerryMage	ba3d6da0c8	load_store_register_unprivileged: bug: LDTRSW	2020-04-22 20:44:38 +01:00
MerryMage	75756137c6	A64: Implement CMEQ (register, vector)	2020-04-22 20:44:38 +01:00
MerryMage	d5283e46e8	IR: Implement IR instructions VectorEqual{8,16,32,64,128}	2020-04-22 20:44:38 +01:00
MerryMage	4ce9c65cfb	reg_alloc: Use std::exchange	2020-04-22 20:44:38 +01:00
Fernando Sahmkow	e0c12ec2ad	A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)	2020-04-22 20:44:38 +01:00
MerryMage	94383fd934	microinstruction: Missed A64{Read,Write}Memory128 from opcode information	2020-04-22 20:44:38 +01:00
MerryMage	d124a1d761	emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable ... For CPUs that didn't support SSE4.1, this was a bug.	2020-04-22 20:44:38 +01:00
James Rowe	589ad7232f	Fixup: Xn|SP are 64 bit addresses encoded in the Rn field	2020-04-22 20:44:38 +01:00
James Rowe	ae880d8391	A64: Fix bugs and address review comments	2020-04-22 20:44:38 +01:00
James Rowe	3aeb7ca50c	Add missing returns	2020-04-22 20:44:38 +01:00
James Rowe	41e6e659c5	A64: Implement Load/Store register (unprivileged)	2020-04-22 20:44:37 +01:00
MerryMage	01a26fa644	fixup: travis: Test with disabled CPU feature detection	2020-04-22 20:44:37 +01:00
Lioncash	5281d3c6d5	CMakeLists: Add opcodes.inc to the source file list ... Allows the file to show up nicely within IDEs	2020-04-22 20:44:37 +01:00
MerryMage	30936f5e94	travis: Test with disabled CPU feature detection ... Ensure that fallbacks are working correctly.	2020-04-22 20:44:37 +01:00
MerryMage	285fd22c30	IR: Add IR instruction VectorZeroUpper	2020-04-22 20:44:37 +01:00
MerryMage	da3e9a5704	a64_emit_x64: bug: EmitA64WriteMemory128 should write not read	2020-04-22 20:44:37 +01:00
FernandoS27	ab84524806	Implemented SDIV and UDIV instructions	2020-04-22 20:44:37 +01:00
MerryMage	6033b05ca6	A64: Implement LDR/STR (immediate, SIMD&FP)	2020-04-22 20:44:37 +01:00
MerryMage	f698848e26	IR: Add IR instructions A64Memory{Read,Write}128 ... Add the Windows ABI implementation	2020-04-22 20:44:37 +01:00
MerryMage	e1df7ae621	IR: Add IR instructions A64Memory{Read,Write}128 ... This implementation only works on macOS and Linux.	2020-04-22 20:44:37 +01:00
MerryMage	e00a522cba	IR: Add IR instruction VectorGetElement{8,16,32,64}	2020-04-22 20:44:37 +01:00
MerryMage	28ccd85e5c	IR: Add IR instruction ZeroExtendToQuad	2020-04-22 20:44:37 +01:00
MerryMage	af848c627d	block_of_code: Add ABI_RETURN2	2020-04-22 20:44:37 +01:00
MerryMage	1749780929	interface: Move Vector typedef to config.h	2020-04-22 20:44:37 +01:00
MerryMage	33bba6028c	bit_util: bug: Infinite loop in HighestSetBit	2020-04-22 20:44:37 +01:00
MerryMage	3caf192f60	A64: Implement DUP (general)	2020-04-22 20:44:37 +01:00
MerryMage	793753bf63	IR: Implement Vector{Lower,}Broadcast{8,16,32,64}	2020-04-22 20:44:37 +01:00
Lioncash	8ee854232c	General: Default constructors and destructors where applicable	2020-04-22 20:44:37 +01:00
Lioncash	d1e4526e1c	ir_emitter: Remove unused includes	2020-04-22 20:44:37 +01:00
Lioncash	6f9216d544	A64: Implement RBIT	2020-04-22 20:44:37 +01:00
MerryMage	9b0a21915f	ir_emitted: Remove unimplemented IR instruction Unimplemented	2020-04-22 20:44:37 +01:00
MerryMage	db30e02ac8	emit_x64: Extract BlockRangeInformation, remove template parameter	2020-04-22 20:44:36 +01:00
MerryMage	58c4a25527	emit_x64: Use JitStateInfo	2020-04-22 20:42:46 +01:00
MerryMage	d4b05b28cf	A64: Implement CLS ... This is not the cleanest implementation.	2020-04-22 20:42:46 +01:00
MerryMage	b8e26bfdc3	A64: Implement ADDP (vector)	2020-04-22 20:42:46 +01:00
MerryMage	eaf545877a	IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}	2020-04-22 20:42:46 +01:00
MerryMage	a554e4a329	backend_x64: Split emit_x64	2020-04-22 20:42:46 +01:00
MerryMage	394bd57bb6	microinstruction: bug: Add missing opcodes	2020-04-22 20:42:46 +01:00
Lioncash	bb1c5bd3b2	A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL	2020-04-22 20:42:46 +01:00
Lioncash	c1a25bfc2f	A64: Implement MADD and MSUB	2020-04-22 20:42:46 +01:00
Lioncash	b7c5055d42	A64: Implement CLZ	2020-04-22 20:42:46 +01:00
Lioncash	b612782445	opcodes: Add 64-bit CountLeadingZeroes opcode	2020-04-22 20:42:46 +01:00
MerryMage	4c4efb2213	data_processing_register: Clean-up	2020-04-22 20:42:46 +01:00
Lioncash	ae5dbcbed6	A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL ... Truly the most difficult A64 instructions to implement.	2020-04-22 20:42:46 +01:00
Lioncash	4d8f4aa8af	A64: Implement ASRV, LSLV, LSRV, and RORV	2020-04-22 20:42:46 +01:00
Lioncash	a8a65beb2b	data_processsing_conditional_select: Implement CSINC, CSINV and CSNEG	2020-04-22 20:42:46 +01:00
Lioncash	b08be71775	a32/a64_emit_x64: Remove unused includes	2020-04-22 20:42:46 +01:00
MerryMage	f81d0a2536	A64: Implement AND (vector)	2020-04-22 20:42:46 +01:00
MerryMage	a63fc6c89b	A64: Implement ADD (vector, vector)	2020-04-22 20:42:46 +01:00
Thomas Guillemard	896cf44f96	A64: Implement REV, REV32, and REV16 (#126)	2020-04-22 20:42:46 +01:00
MerryMage	5eb0bdecdf	IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 ... ARM's Architecture Specification Language doesn't distinguish between floats and integers as much as we do. This makes some things difficult to implement. Since our register allocator is now capable of allocating values to XMMs and GPRs as necessary, the Transfer IR instructions are no longer necessary as they used to be and they can be removed.	2020-04-22 20:42:46 +01:00
MerryMage	9a812b0c61	reg_alloc: GetBitWidth: Add UNREACHABLE	2020-04-22 20:42:46 +01:00
MerryMage	fff8e019dc	reg_alloc: Consider bitwidth of data and registers when emitting instructions	2020-04-22 20:42:46 +01:00
MerryMage	144b629d8a	A64: Implement CSEL	2020-04-22 20:42:45 +01:00
MerryMage	6395f09f94	IR: Implement Conditional Select	2020-04-22 20:42:45 +01:00
MerryMage	19da68568e	A64/translate/branch: bug: Read-after-write error in BLR	2020-04-22 20:42:45 +01:00
MerryMage	9f57283a30	A64: Implement SBFM, BFM, UBFM	2020-04-22 20:42:45 +01:00
MerryMage	cdbc8d07a5	A64: Implement MOVN, MOVZ, MOVK	2020-04-22 20:42:45 +01:00
MerryMage	ecebe14a01	ir/location_descriptor: Add missing <functional> header for std::hash	2020-04-22 20:42:45 +01:00
MerryMage	4e3675da7b	a64_merge_interpret_blocks: Remove debug output	2020-04-22 20:42:45 +01:00
MerryMage	c6a091d874	A64: Optimization: Merge interpret blocks	2020-04-22 20:42:45 +01:00
MerryMage	21fe61eac6	A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate	2020-04-22 20:42:45 +01:00
MerryMage	7c4b70751c	A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31	2020-04-22 20:42:45 +01:00
MerryMage	996ffd5488	a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers	2020-04-22 20:42:45 +01:00
MerryMage	e4615a4562	emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64	2020-04-22 20:42:45 +01:00
MerryMage	0992987c98	A64: Add ExceptionRaised IR instruction ... The purpose of this instruction is to raise exceptions when certain decode-time issues happen, instead of asserting at translate time. This allows us to use the translator for code analysis without worrying about unnecessary asserts, but also provides flexibility for the library user to perform custom behaviour when one of these states are raised.	2020-04-22 20:42:45 +01:00
MerryMage	61125d6dd1	A64/translate: Add TranslateSingleInstruction function	2020-04-22 20:42:45 +01:00
MerryMage	aa74a8130b	Misc. fixups of MSVC build	2020-04-22 20:42:45 +01:00
MerryMage	a1dfa01515	imm: Suppress MSVC warning C4244: value will never be truncated	2020-04-22 20:42:45 +01:00
MerryMage	26da149639	imm: compiler bug: MSVC 19.12 with /permissive- flag doesn't support fold expressions	2020-04-22 20:42:45 +01:00
MerryMage	b34c6616d4	A64/decoder: Split decoder data from header	2020-04-22 20:42:45 +01:00
MerryMage	72a793f5b0	ir_opt: Split off A32 specific passes	2020-04-22 20:42:45 +01:00
MerryMage	595f157e5e	A64: Implement LDP, STP	2020-04-22 20:42:45 +01:00
MerryMage	511215342b	A64/location_descriptor: Fix -fpermissive warning on GCC	2020-04-22 20:42:45 +01:00
MerryMage	243f06c613	A64: Implement LDP, STP	2020-04-22 20:42:45 +01:00
MerryMage	25411da838	A32: Implement load stores (immediate)	2020-04-22 20:42:45 +01:00
MerryMage	2aadeec291	A64: Implement SVC	2020-04-22 20:42:45 +01:00
MerryMage	9e27e4d250	imm: bug: SignExtend wasn't working for T with bit size > 32	2020-04-22 20:42:45 +01:00
MerryMage	10c60dda97	a64_emit_x64: Don't use far code for now	2020-04-22 20:42:45 +01:00
MerryMage	593a569b53	EmitA64SetW: bug: should zero extend to entire 64-bit register	2020-04-22 20:42:45 +01:00
MerryMage	6bd9f02911	EmitA64SetNZCV: bug: to_store is scratch	2020-04-22 20:42:45 +01:00
MerryMage	f0276dd53b	emit_x86: Fix nzcv for EmitSub	2020-04-22 20:42:45 +01:00
MerryMage	68391b0a05	A64: Implement SVC	2020-04-22 20:42:45 +01:00
MerryMage	e5ace37560	a64_emit_x64: Call interpreter	2020-04-22 20:42:45 +01:00
MerryMage	b12dead76a	A64: Add batch register retrieval to interface	2020-04-22 20:42:45 +01:00
MerryMage	cb481a3a48	A64: Implement compare and branch	2020-04-22 20:42:45 +01:00
MerryMage	e8bcf72ee5	A64: PSTATE access and tests	2020-04-22 20:42:45 +01:00
MerryMage	23f3afe0b3	A64: Implement branch (register)	2020-04-22 20:42:45 +01:00
MerryMage	86d1095df7	A64: Implement branch	2020-04-22 20:42:45 +01:00
MerryMage	0641445e51	A64: Implement logical	2020-04-22 20:42:45 +01:00
MerryMage	5a1d88c5dc	A64: Implement pcrel	2020-04-22 20:42:45 +01:00
MerryMage	c09e69bb97	A64: Implement addsub instructions	2020-04-22 20:42:44 +01:00
MerryMage	d1cef6ffb0	A64: Implement ADD_shifted	2020-04-22 20:42:44 +01:00
MerryMage	d1eb757f93	A64: Backend framework	2020-04-22 20:42:44 +01:00
MerryMage	e161cf16f5	A64: Initial framework	2020-04-22 20:42:44 +01:00
MerryMage	f61da0b5a9	IR: Compile-time type-checking of IR	2020-04-22 20:39:27 +01:00
MerryMage	44f7f04b5c	IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg	2020-04-22 20:39:27 +01:00
MerryMage	83022322d1	Make IR->A32 LocationDescriptor conversion explicit	2020-04-22 20:39:27 +01:00
MerryMage	9d15e0a8e1	Final A32 refactor	2020-04-22 20:39:27 +01:00
MerryMage	455757d7b6	EmitX64: JitState type as template parameter	2020-04-22 20:39:26 +01:00
MerryMage	2d164d9345	Package up emit context	2020-04-22 20:38:31 +01:00
MerryMage	7bf421dd38	Rename JitState to A32JitState	2020-04-22 20:38:31 +01:00
MerryMage	63bd1ece23	backend_x64: Split A32 specific emission into separate class	2020-04-22 20:38:29 +01:00
MerryMage	8bef20c24d	IR: Split off A32 specific opcodes	2020-04-22 20:33:32 +01:00
MerryMage	b1f0cf9278	A32: Split off A32 specific IREmitter	2020-04-22 20:33:32 +01:00
MerryMage	b3c73e2622	Label A32 specific code appropriately	2020-04-22 20:33:30 +01:00
MerryMage	dc357c780d	EmitPackedHalvingSub{U,S}16: SSE2 implementation	2020-04-22 20:27:15 +01:00
MerryMage	a98821da41	Merge branch 'misc' ... These commits introduce context save and restore, and a small number of optimizations that depend on their use for performance.	2020-04-22 20:27:15 +01:00
MerryMage	fc885ac80f	EmitPackedHalvingAddU8: Add SSE2 implementation	2020-04-22 20:27:15 +01:00
MerryMage	4682211729	EmitPackedHalvingAdd{U,S}16: Add SSE2 implementation	2020-04-22 20:27:15 +01:00
MerryMage	9ac1c87a51	emit_x64: EmitSet{Register,ExtendedRegister32,ExtendedRegister64}: Store from current source	2020-04-22 20:27:15 +01:00
MerryMage	6e834de072	Add re-entry prediction to avoid std::unordered_map lookups	2020-04-22 20:26:40 +01:00
MerryMage	984ce22431	emit_x64: Arguments to MostSignificantBit and IsZero are 32-bit	2020-04-22 20:26:40 +01:00
MerryMage	5c6fcf378f	emit_x64: Optimize code emitted by EmitGetCpsr	2020-04-22 20:26:40 +01:00
MerryMage	f595f85039	block_of_code: Remove vzeroupper	2020-04-22 20:26:40 +01:00
MerryMage	4393473d06	interface: Allow saving and storing of contexts	2020-04-22 20:26:40 +01:00
MerryMage	05f3f07704	emit_x64: Reduce mxscr operations in EmitGetFpscr and EmitSetFpscr	2020-04-22 20:26:40 +01:00
MerryMage	19a7fb8992	jit_state: Split off CPSR.NZCV	2020-04-22 20:26:40 +01:00
MerryMage	0af1e7723d	CMakeLists: Fixup boost ... * boost is part of the public interface. * Consider boost a system library so warnings from boost do not cause a build failure. * If the parent project defines boost, use that.	2020-04-22 20:26:40 +01:00
MerryMage	a3432102b8	jit_state: Split off CPSR.Q	2020-04-22 20:26:40 +01:00
MerryMage	4f8675083c	interface_x64: Fix MSVC cast warning	2020-04-22 20:26:40 +01:00
MerryMage	311361b409	jit_state: Split off CPSR.{E,T} ... This allows us to improve code-emission for PopRSBHint. We also improve code emission other terminals at the same time.	2020-04-22 20:26:40 +01:00
MerryMage	cb119c2f72	emit_x64: Use boost::icl::interval_map to speed up ranged invalidation	2020-04-22 20:26:40 +01:00
MerryMage	3cca3bbd0b	jit_state: Split off CPSR.GE	2020-04-22 20:26:40 +01:00
MerryMage	6fde29f5d8	emit_x64: Remove unnecessary ABI overhead in ReadMemory, WriteMemory	2020-04-22 20:26:40 +01:00
MerryMage	6adc554b53	jit_state: Hide cpsr implementation	2020-04-22 20:26:40 +01:00
MerryMage	eb80aae9c0	block_of_code: Move MXCSR switching out of dispatch loop ... Also clarify MXCSR entry/exit terminology	2020-04-22 20:26:40 +01:00
MerryMage	a4e85ad565	emit_x64: Make RSB a stack	2020-04-22 20:26:40 +01:00
MerryMage	2a818f9d8e	Merge branch 'timing' ... We do this to improve timing information before entering a supervior function. We also do this to try and stay within JITted code as much as possible, by updating the cycles we have remaining.	2020-04-22 20:26:37 +01:00
MerryMage	ea4c3292d5	BlockOfCode: Detect space remaining ... We also clear the code cache when we run out of space. This closes #111.	2020-04-22 20:26:12 +01:00
MerryMage	256749910f	Add AddTicks and GetTicksRemaining callbacks	2020-04-22 20:26:12 +01:00
MerryMage	80c56aa89d	Remove unnecessary use of boost::make_optional ... Closes #119.	2020-04-22 20:26:12 +01:00
MerryMage	de6a93a160	decoder_detail: Lambda captures may be unused if iota is an empty sequence ... Closes #120	2020-04-22 20:26:12 +01:00
MerryMage	3141dadea9	Remove UNUSED macro	2020-04-22 20:26:12 +01:00
MerryMage	7cac9519b0	microinstruction: Remove DecrementRemainingUses	2020-04-22 20:26:12 +01:00
MerryMage	639f7cfd2d	reg_alloc: Add IsLastUse optimization for UseScratch	2020-04-22 20:26:12 +01:00
MerryMage	6b122751fe	reg_alloc: Remove reliance on IR::Inst::DecrementRemainingUses	2020-04-22 20:26:12 +01:00
MerryMage	30049ca928	emit_x86: Standardize time of DefineValue call	2020-04-22 20:26:12 +01:00
MerryMage	5d72f7048f	basic_block: Add inst address and use count to DumpBlock ... This additional output assists with debugging.	2020-04-22 20:26:12 +01:00
Mat M	c6d09adcb7	CMakeLists: Derive the source file listings from targets directly (#118) ... This gets rid of the need to store to individual variables before creating the target itself, cleaning up the variables in the surrounding scope a little bit.	2020-04-22 20:26:07 +01:00
MerryMage	12eaf496fd	emit_x64: Perform mask creation for packed instructions in SSE	2020-04-22 20:26:07 +01:00
MerryMage	305e4baa29	emit_x64: Eliminate conversion of GE flags ... * We do this so that we can simplify PackedSelect. * We also try to minimise xmm-gpr/gpr-xmm transfers in PackedSelect.	2020-04-22 20:26:07 +01:00
MerryMage	d1e0a29cd9	Implement IR instruction PackedSelect, reimplement SEL	2020-04-22 20:26:07 +01:00
MerryMage	18f11972c6	emit_x64: Remove SSSE3 implementation of PackedHalvingAddU8 ... It is much slower than the SSE2 implementation, so there's no point keeping it around.	2020-04-22 20:26:07 +01:00
MerryMage	c4b40909f7	emit_x64: Improve code emission of FPCompare{32,64} ... Replace if-chain with table lookup	2020-04-22 20:26:07 +01:00
MerryMage	814e378249	VCMP and VCMPE were the other way around ... - This was due to a misunderstanding of what the E in VCMPE means. - The E refers to an exception being raised when a QNaN is encountered. - Added unit tests for VCMP{E}	2020-04-22 20:26:07 +01:00
MerryMage	08f638d447	emit_x64: pmaxuw and pminuw require SSE 4.1 ... This commit is intended to close citra-emu/citra#3137. pmaxuw and pminuw were used to perform unsigned comparisons; we emulate these using a signed comparison by offsetting the inputs by 0x8000 for CPUs that do not support SSE 4.1.	2020-04-22 20:26:07 +01:00
Mat M	522992965a	Common: Delete Pool's copy constructor and copy/move assignment operators (#117) ... The language defines a copy constructor as: TypeName(const TypeName&) so this was just deleting a constructor variant that would catch most cases of attempted copies.	2020-04-22 20:22:01 +01:00
Mat M	77fe2aeeaa	emit_x64: Amend doxygen parameters for InvalidateCacheRange() (#116)	2020-04-22 20:22:01 +01:00
MerryMage	19dcdde90b	block_of_code: Add vzeroupper instructions where AVX-SSE transitions may occur	2020-04-22 20:22:01 +01:00
MerryMage	60d9392b5c	block_of_code: BlockOfCode should provide cpu info	2020-04-22 20:22:01 +01:00
MerryMage	148c01e08f	interface_x64: Remove is_executing assert from HaltExecution ... In multithreaded code this can be triggered due to a race.	2017-10-14 23:35:01 +01:00
MerryMage	f6cf265bc5	block_of_code: BlockOfCode::ABI_* should be const	2017-09-29 01:35:24 +01:00
MerryMage	29471be317	Standardize location of storage-class specifiers: Place at beginning of declarations ... Justification: C99 specifies that doing otherwise is an obsolescent feature.	2017-09-29 01:23:45 +01:00
MerryMage	b992e5f8ec	Ranged cache invalidation ... * Fix clearing code block on a partial invalidation * Remove unnecessary use of boost::variant * Code cleanup	2017-09-11 00:11:05 +01:00
Lioncash	80477b5a67	externals: update fmt to 4.0	2017-08-27 21:43:21 +01:00
MerryMage	568b52d4ba	externals: Update Xbyak to v5.51 ... Xbyak now supports multi-byte nops	2017-08-17 21:34:54 +01:00
MerryMage	1613846ab0	reg_alloc: Handle XMM registers in LoadImmediate	2017-08-16 23:11:05 +01:00
MerryMage	993e142c6b	disassembler: Fix RegList	2017-08-05 01:57:29 +01:00
MerryMage	6197bde0fc	disassembler_arm: Fix disassembly of LDRH (reg)	2017-07-30 18:45:55 +01:00
Yuri Kunde Schlesner	38eb7e0314	emit_x64: Use alternative Xbyak names for and, or, xor ... Also enabled XBYAK_NO_OP_NAMES, allowing us to stop using -fno-operator-names.	2017-06-12 07:57:46 +01:00
James Rowe	82e8c99a47	Link against static fmtlib instead of header only ... When including fmtlib as a header only library in dynarmic, downstream projects cannot include fmtlib as a static library without getting linker errors.	2017-05-22 08:23:03 +01:00
MerryMage	599a613fea	Move SEL from status_register_access to misc	2017-04-25 13:57:27 +01:00
MerryMage	50bb317104	parallel: UQADD8 and UQADD16 are unpredictable when {d|n|m} == 15	2017-04-25 13:45:31 +01:00
MerryMage	7639dfea51	coprocessor: Use && instead of & with boolean arguments	2017-04-22 15:05:31 +01:00
MerryMage	2c9dcfa2db	backend_x64: Rename UnwindHandler to ExceptionHandler	2017-04-20 14:08:56 +01:00
MerryMage	0d47f50f57	block_of_code: Implement farcode	2017-04-19 18:58:36 +01:00
MerryMage	1c21ae6bcd	saturated: Implement QASX, QSAX, UQASX, UQSAX	2017-04-10 10:21:51 +01:00
MerryMage	9ac890c62d	reg_alloc: Fix for LLVM's interpretation of the System V ABI ... This aspect of the System V ABI is under-defined. LLVM choses a different interpretation from GCC and ICC. Most other compilers assume the callee is responsible zero-ing the upper bits of the register if necessary. LLVM assumes the caller has zero-extended the register. This is a quick fix for this problem until zext-tracking is implemented.	2017-04-08 22:12:37 +01:00
MerryMage	a5bb81a97c	backend_x64: Remove dispatch loop in Jit::Run	2017-04-08 10:04:53 +01:00
MerryMage	1b37420459	backend_x64: Simplify dispatcher	2017-04-08 09:35:45 +01:00
MerryMage	523ae542f4	microinstruction: Implement HasAssociatedPseudoOperation	2017-04-04 13:10:50 +01:00
MerryMage	4c5de3905b	emit_x64: Correct mutation of immutable in FPThreeOp{32,64} ... operand (args[1]) was erroneously declared as non-scratch. operand's value could be modified if FTZ was enabled.	2017-04-01 09:57:14 +01:00
MerryMage	05e97058c3	parallel: Add and Subtract with Exchange improvements ... * Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction * Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions * Implement SASX, SSAX, UASX, USAX	2017-03-24 15:56:24 +00:00
Lynn	fd068ed6b8	Ranged cache invalidation	2017-03-20 11:58:25 +00:00
MerryMage	d9c69ad997	constant_pool: Implement a constant pool	2017-03-19 13:08:04 +00:00
Lioncash	5a02da445a	CMakeLists: Only link LLVM libs against the library ... LLVM library code is only used within the main dynarmic library, not the test executable.	2017-03-11 13:25:14 +00:00
Lioncash	d85137ed65	interface_x64: Amend LLVM disassembly code ... This would previously attempt to perform pointer arithmetic on void pointers, which would cause compilation errors.	2017-03-07 18:32:04 +00:00
Lioncash	d0efbb9348	CMakeLists: Remove unnecessary linker language specifiers ... This is already inferred by the cmake project being declared a CXX project.	2017-03-07 18:30:58 +00:00
Lioncash	9906be746f	CMakeLists: Make boost an interface library target ... Gets rid of the use of a non-target include and makes libraries explicitly link against the identifier name in order to get includes.	2017-03-04 11:52:32 +00:00
MerryMage	6396bd02f0	Merge branch 'simplify-reg-alloc'	2017-02-27 00:11:52 +00:00
MerryMage	92a01b0cd8	Prefer ASSERT to DEBUG_ASSERT	2017-02-26 23:30:40 +00:00
MerryMage	135346eb2e	reg_alloc: Move implementations out of header	2017-02-26 23:30:39 +00:00
MerryMage	184db36caf	reg_alloc: Call DecrementRemainingUses in only one place	2017-02-26 23:30:38 +00:00
MerryMage	51fc9fec05	reg_alloc: Reorganize	2017-02-26 23:30:37 +00:00
MerryMage	cf93ab3d31	reg_alloc: Remove old register allocator interface	2017-02-26 23:12:26 +00:00
MerryMage	08a467bf9a	emit_x64: Port to new register allocator interface	2017-02-26 23:12:25 +00:00
Lioncash	662e07337f	CMakeLists: Don't explicitly signify dynarmic as a static lib ... This allows a user of the library to explicitly control which kind of library type should be built with the CMake BUILD_SHARED_LIBS flag. By default, libraries will build as static without this specifier.	2017-02-26 23:08:49 +00:00
MerryMage	f883bad2cc	reg_alloc: New register allocation interface	2017-02-26 21:37:35 +00:00
MerryMage	13ac0c234e	reg_alloc: Differentiate between ReadLock and WriteLock	2017-02-26 21:37:34 +00:00
MerryMage	6c3df057fa	reg_alloc: Remove unused functions	2017-02-26 21:37:33 +00:00
MerryMage	1ee4c07f14	reg_alloc: Reimplement ScratchHostLocReg	2017-02-26 21:37:32 +00:00
MerryMage	640faab8a7	reg_alloc: UseHostLoc is no longer necessary	2017-02-26 21:37:30 +00:00
MerryMage	9518bbe06e	reg_alloc: Reimplement UseScratchHostLocReg	2017-02-26 21:37:29 +00:00
MerryMage	e1d8238c50	reg_alloc: Stub UseOpArg	2017-02-26 21:37:27 +00:00
MerryMage	2b078152e7	reg_alloc: Reimplement UseHostLocReg	2017-02-26 21:37:26 +00:00
MerryMage	aefe550428	reg_alloc: Remove the Def concept from register allocator internals	2017-02-26 21:37:25 +00:00
MerryMage	65cccf070e	reg_alloc: Properly encapsulate HostLocInfo	2017-02-26 21:37:24 +00:00
MerryMage	469bb6253f	backend_x64: Factor EmitExclusiveWriteMemory64 into ExclusiveWrite	2017-02-26 15:34:26 +00:00
MerryMage	d7ab1f9c64	backend_x64: Fix ABI violation in ReadMemory and WriteMemory ... Caller-save registers were not saved before call instruction. Refer to issue #98.	2017-02-26 15:34:25 +00:00
MerryMage	3768174783	ir_opt: Constant propagation pass works better with a DCE just before it	2017-02-26 15:28:35 +00:00
MerryMage	157585887e	ir_opt: Simplify dead-code elimination pass	2017-02-26 15:28:34 +00:00
MerryMage	bbeea72eba	ir_opt: Remove redundant shift instructions	2017-02-26 15:28:14 +00:00
MerryMage	517fe0f18e	emit_x64: WriteMemory* microinstructions do not define a value	2017-02-25 11:54:47 +00:00
MerryMage	1ff60bc69f	reg_alloc: Move OpArg into own header	2017-02-21 23:38:36 +00:00
MerryMage	4ed8ee7489	microinstruction: Void arguments when invalidating instruction	2017-02-18 21:29:23 +00:00
MerryMage	7fa5845c1f	extension: Implement SXTAB16 and SXTB16	2017-02-18 20:14:44 +00:00
MerryMage	73d1cf36c3	extension: Simplify UXTB16	2017-02-18 20:14:39 +00:00
MerryMage	6edcfeba0b	extension: Simplify rotation code	2017-02-18 20:14:37 +00:00
MerryMage	cc9d2c4603	saturated: Implement SSAT16 and USAT16	2017-02-18 17:43:57 +00:00
MerryMage	358cf7c322	vfp: Implement vectorized VFP instructions	2017-02-18 01:13:25 +00:00
MerryMage	f2dd82967f	load_store: Simplify implementation ... * Remove dead code * Standardise code style with rest of code base	2017-02-16 22:28:56 +00:00
MerryMage	058f7b5de6	emit_x64: Make EmitTerminal type-safe ... Avoid the use of boost::variant::which, which tends to produce code which is not verifiable at compile-time.	2017-02-16 19:40:51 +00:00
MerryMage	e197b10b96	common: Introduce utility function VisitVariant ... VisitVariant allows one to use a generic lambda to visit a boost::variant. This is necessary because boost::visit_variant requires the visitor type to provide a return type.	2017-02-16 19:30:56 +00:00
MerryMage	5a20a37d3f	arm/fpscr: Correct Stride implementation	2017-02-11 12:13:57 +00:00
MerryMage	033e8b9b1e	vfp: Rename variables a, b, c to more sensible names	2017-02-06 21:14:36 +00:00
MerryMage	2af39dfaa8	emit_x64: Make reg_alloc a local variable ... reg_alloc contains state that is only valid on a per-block basis, so there is no reason for it to be a member variable.	2017-02-04 09:29:35 +00:00
MerryMage	a0e9417912	ir_opt: Initial constant propagation pass implementation	2017-01-30 21:49:46 +00:00
MerryMage	2447f2f360	callbacks: Factorize memory callbacks into inner structure	2017-01-30 21:42:51 +00:00
MerryMage	642ccb0f66	ir/value: Support U16 immediates	2017-01-29 22:58:11 +00:00
MerryMage	5f7ffe0d0b	microinstruction: Implement Inst::AreAllArgsImmediates	2017-01-29 22:56:59 +00:00
MerryMage	22804dc6a5	microinstruction: Arguments of Inst::Use and Inst::UndoUse should be const	2017-01-29 22:53:46 +00:00
MerryMage	1d4446cad5	microinstruction: Removed unnecessary reference from argument of Inst::ReplaceUsesWith	2017-01-29 22:52:33 +00:00
MerryMage	3e0e339d98	bit_util: Remove unnecessary include	2017-01-09 22:19:51 +00:00
MerryMage	9ecdd32b84	coprocessor: Implement fast-path for Coproc{Send,Get}{OneWord,TwoWords} ... Allow coprocessor interface to provide pointers instead of a callback. This allows for a fastpath when all that is required is to read or write a value and no other action needs to be taken.	2017-01-08 14:56:06 +00:00
MerryMage	e3bc7d039f	Implement CDP, LDC, MCR, MCRR, MRC, MRRC, STC	2017-01-08 14:56:06 +00:00
MerryMage	48693eb6ff	Implement coprocessor-related microinstructions ... * CoprocInternalOperation * CoprocSendOneWord * CoprocSendTwoWords * CoprocGetOneWord * CoprocGetTwoWords * CoprocLoadWords * CoprocStoreWords	2017-01-08 14:56:06 +00:00
MerryMage	b3ae57619d	types: Formatting for CoprogReg	2017-01-08 14:56:06 +00:00
MerryMage	d8a37e287c	IR: Add IR type CoprocInfo	2017-01-08 14:56:06 +00:00
MerryMage	890b2f75ad	callbacks: Add coprocessor interface	2017-01-08 14:56:06 +00:00
MerryMage	1efd3a764d	IR: Remove unused microinstructions NegateLowWord and NegateHighWord	2017-01-05 20:16:39 +00:00
Fernando Sahmkow	70f4235ee9	Implement UXTAB16 (#78)	2016-12-29 12:15:18 +00:00
MerryMage	0d1fa85402	bit_util: Bit<T>(size_t, const T) cannot be constexpr ... Compound statements are not permitted in constexpr functions in C++14	2016-12-29 10:08:35 +00:00
FernandoS27	d5610eb26c	Implement UHASX, UHSAX, SHASX and SHSAX (#75)	2016-12-28 21:32:22 +00:00
MerryMage	e9df248d56	decoder_detail: Support const member functions	2016-12-23 11:33:40 +00:00
MerryMage	163b67bf1f	mp: Add support for const member function pointers to FunctionInfo	2016-12-23 11:32:12 +00:00
MerryMage	b1bad4b5cc	decoder_detail: static_assert member function is from visitor class ... Improves readability of compiler errors.	2016-12-23 11:10:02 +00:00
MerryMage	c7e5216473	emit_x64: EraseInstruction now also invalidates the instruction ... There is now no longer a need to call DecrementRemainingUses on the parent instruction.	2016-12-22 18:43:11 +00:00
MerryMage	c78f153ddb	decoder/arm: Sort decoders according to number of bits in mask	2016-12-22 15:25:38 +00:00
MerryMage	cb38c94b58	decoder/arm: Fix decoding of RFE	2016-12-22 15:25:07 +00:00
MerryMage	7e77ee7fd6	decoder/arm: Fix decoding of MCR2	2016-12-22 15:11:47 +00:00
Fernando Sahmkow	677f62dd6f	Implement SHSUB8 and SHSUB16 (#74) ... * Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16	2016-12-22 12:02:24 +00:00
MerryMage	967f3cf7e1	Implement CPS (Thumb) ... * Since currently only User mode is emulated, CPS is a NOP.	2016-12-21 22:44:27 +00:00
MerryMage	c764a2b889	Implement MUL (T1)	2016-12-21 22:44:14 +00:00
MerryMage	36082087de	callbacks: Read code using MemoryReadCode callback	2016-12-21 21:39:14 +00:00
MerryMage	56ea2386d3	saturated: Implement SSAT and USAT	2016-12-21 19:51:25 +00:00
MerryMage	6a269a6ebd	IR: Add microinstructions UnsignedSaturation and SignedSaturation	2016-12-21 19:51:25 +00:00
MerryMage	b23b524b03	bit_util: Add SignExtend implementation with runtime bit_count argument	2016-12-21 19:51:25 +00:00
MerryMage	02b2ab7581	emit_x64: Pass tmp to ExtractMostSignificantBitFromPackedBytes in EmitPackedAddU8	2016-12-20 22:07:51 +00:00
MerryMage	097f6a83da	emit_x64: Document ExtractAndDuplicateMostSignificantBitFromPackedWords	2016-12-20 22:06:14 +00:00
MerryMage	03f168094d	emit_x64: Document ExtractMostSignificantBitFromPackedBytes	2016-12-20 22:05:51 +00:00
FernandoS27	8919265d2c	Implement SADD8, SADD16, SSUB8, SSUB16, USUB16	2016-12-20 21:52:38 +00:00
FernandoS27	3f6ecfe245	Implemented USAD8 and USADA8	2016-12-20 21:52:38 +00:00
MerryMage	b1d3e7aae9	emit_x64: Refactor patching code ... * Only have a single std::unordered_map for patching information * Factor patch emitters into own functions * Implement EmitX64::Unpatch	2016-12-20 14:06:55 +00:00
MerryMage	cc58666c06	CMakeLists: Use target_compile_options intead of add_compile_options	2016-12-19 00:48:25 +00:00
MerryMage	74a95ea51e	block_of_code: Rename alloc to AllocateFromCodeSpace	2016-12-18 23:43:48 +00:00
MerryMage	96e46ba6b5	Implement QADD, QSUB, QDADD, QDSUB	2016-12-15 22:34:29 +00:00
MerryMage	b178ab3bec	Replace (void)(...); idiom with UNUSED macro	2016-12-15 21:36:05 +00:00
MerryMage	276873bf70	Wrap #pragma warning with #ifdef _MSC_VER .. #endif	2016-12-15 21:36:02 +00:00
MerryMage	0e8b626d87	CMakeLists: Globally disable MSVC warning C4592 ... C4592: Symbol will be dynamically initialized (implementation limitation)	2016-12-15 21:09:55 +00:00
MerryMage	91e851a991	CMakeLists: Enable /W4 on MSVC	2016-12-15 20:52:23 +00:00
MerryMage	63caed7b09	emit_x64: Remove argument names of unused arguments	2016-12-15 20:52:22 +00:00
MerryMage	df197ff6b1	arm/types: Use smallest possible standard type that has sufficient bits for Imm{} types	2016-12-15 20:52:21 +00:00
MerryMage	546198d603	translate_arm: Mark arguments as unused	2016-12-15 20:52:20 +00:00
MerryMage	8d5522f4a0	dissassembler_arm: Support BKPT, QASX, QSAX, UQASX, UQSAX	2016-12-15 20:16:08 +00:00
Yuri Kunde Schlesner	34e19f135c	CMake: Re-use external xbyak target if present (#62)	2016-12-12 14:23:42 +00:00
MerryMage	5bea2e1680	block_of_code: Support stack unwinding on Windows	2016-12-12 07:49:18 +00:00
MerryMage	4962d92b79	block_of_code: Do not regenerate prelude when clearing cache	2016-12-12 07:49:18 +00:00
MerryMage	2a1cf94b1c	CMakeLists: Include backend_x64 only if we're targeting x86_64	2016-12-12 07:49:18 +00:00
MerryMage	dcc880a002	assert: _a_ expression string shouldn't be part of the format string ... The expression may contain the % operator.	2016-12-12 07:49:18 +00:00
MerryMage	179a3388f9	block_of_code: Provide an alloc function to allocate space in the code block	2016-12-12 07:49:18 +00:00
Lioncash	f467589346	emit_x64: Remove unnecessary casts	2016-12-05 20:30:19 +00:00
Lioncash	a37631c010	emit_x64: Use reinterpret_cast for pointer casts	2016-12-05 20:30:19 +00:00
Lioncash	fafa845f64	emit_x64: Make GetBasicBlock() const qualified	2016-12-05 12:46:22 +00:00
Lioncash	6a16edc0fb	emit_x64: Move implementations into the cpp file ... Prevents needing to rebuild everything including the emitter if any details ever change.	2016-12-05 12:46:22 +00:00
Lioncash	282029f60a	emit_x64: Forward declare BlockOfCode	2016-12-05 12:46:22 +00:00
Lioncash	6898b74c78	emit_x64: Get rid of indirect includes	2016-12-05 12:46:22 +00:00
MerryMage	54d051977f	emit_x64: Use movdqa instead of movaps in EmitPackedSubU8 ... While movaps and movdqa are behaviourly equivalent, using movaps may incur a domain crossing penalty on some microarchitectures. This is because movaps is an instruction in the floating-point domain while the following instructions are in the integer domain.	2016-12-05 01:00:51 +00:00
MerryMage	52e1445f43	Implement USUB8	2016-12-05 00:29:15 +00:00
MerryMage	5c1aab1666	Implement CLZ ... Includes tests	2016-12-04 22:56:33 +00:00
MerryMage	1a1646d962	Implement UADD8	2016-12-04 20:52:33 +00:00
MerryMage	7cad6949e7	IR: Implement new pseudo-operation GetGEFromOp	2016-12-04 20:52:06 +00:00
MerryMage	25f21b5371	emit_x64: Inline nzcv computation into EmitFPCompare32 and EmitFPCompare64	2016-12-04 11:43:31 +00:00
MerryMage	cede5e442a	emit_x64: Use xorps/xorpd when argument to TransferToFP32/TransferToFP64 is an immediate zero	2016-12-03 11:41:10 +00:00
MerryMage	e166965f3e	Implement VCMP	2016-12-03 11:41:09 +00:00
MerryMage	f2fe376fc6	Support 64-bit immediates	2016-12-03 11:29:50 +00:00
Mat M	95f34c683c	reg_alloc: Remove unnecessary breaks after returns (#54)	2016-12-02 19:14:44 +00:00
Mat M	de1f831d79	microinstruction: Make use_count private (#53) ... Makes the operation a part of the direct interface.	2016-11-30 21:51:06 +00:00
MerryMage	3621a925b2	reg_alloc: Register allocator related constraints belong with the rest of the register allocator ... HostLocToReg64 contained two DEBUG_ASSERTs invloving constraints that really belonged to the register allocator. The register allocator prevents allocation of RSP and R15 because those are reserved for the stack pointer and the state pointer respectively.	2016-11-30 19:42:41 +00:00
MerryMage	5f11b4f50e	HostLoc: R15 is a GPR	2016-11-30 18:38:03 +00:00
Sebastian Valle	14eb70d7e4	VFP: Fixed the VCVT behavior when converting from unsigned 32-bit values. (#51) ... Use a 64-bit register to hold the values so that we don't end up interpreting them as signed values.	2016-11-27 23:25:50 +00:00
Merry	0ff8c375af	Implement UHSUB8 and UHSUB16 (#48)	2016-11-26 18:27:21 +00:00
Merry	cb17f9a3ed	Implement SHADD8 and SHADD16 (#47)	2016-11-26 18:12:29 +00:00
Sebastian Valle	11ae8d1ffa	Added disassembler support for the ARM parallel add/subtract (modulo arithmetic) instructions. (#50)	2016-11-26 17:58:09 +00:00
Sebastian Valle	ed71e31cea	Added disassembler support for the ARM parallel and saturated instructions (#44)	2016-11-26 17:49:46 +00:00
MerryMage	c0c1bb1094	Implemented UHADD16	2016-11-26 11:28:20 +00:00
Mat M	4f7dc81492	mp: Fix static_assert condition (#46) ... Not an issue currently, but this would have prevented type inspection on the last function parameter.	2016-11-25 22:09:45 +00:00
Yuri Kunde Schlesner	9ec51f74bd	libfmt: Update version to current master	2016-11-25 20:47:04 +00:00
Sebastian Valle	4d44474ad4	Implemented the ARM UHADD8 instruction. (#45) ... The x64 implementation uses the SSSE3 instruction PSHUFB. A non-SSE fallback is provided in case the CPU doesn't support it.	2016-11-25 20:32:22 +00:00
Sebastian Valle	f32921d493	ARM: Implemented UXTB16. (#42) ... It passes tests.	2016-11-24 08:21:12 +00:00
Sebastian Valle	32615d0eff	Implemented the PKHTB and PKHBT instructions with tests. (#40)	2016-11-23 21:45:18 +00:00
MerryMage	780ff8e00e	status_register_access: SEL: Use GetGEFlags	2016-11-23 19:47:35 +00:00
MerryMage	b6f7b8babd	ir: Implement GetGEFlags, SetGEFlags	2016-11-23 19:44:27 +00:00
MerryMage	e7d02a5439	get_set_elimination_pass: Refactor CPSR related eliminations	2016-11-23 18:42:13 +00:00
Sebastian Valle	d589c63107	Implemented the ARM SEL instruction, with tests. (#39) ... The test for this instruction is very peculiar. As the instruction's behavior depends on the value of the CPSR, we generate a MSR instruction after each SEL instruction to change the CPSR.	2016-11-23 18:14:07 +00:00
Mat M	65dcf45ca6	FPSCR: Mask away reserved bits (#34)	2016-09-21 17:51:13 +01:00
MerryMage	792f2bfd94	translate_arm: Remove unused method ArmTranslatorVisitor::LinkToNextInstruction	2016-09-21 14:07:53 +01:00
Mat M	f75acd6cfb	decoder: Generify the matcher interface (#33) ... Gets rid of a bit of duplication while remaining compatible with the current interfaces in place.	2016-09-17 09:48:18 +01:00
Mat M	943487ecee	disassembler: Provide includes to function declarations (#32)	2016-09-14 23:03:09 +01:00
Mat M	72897b5def	types: Provide ostream operator<< overloads where applicable (#30)	2016-09-07 14:21:17 +01:00
Mat M	b41de890fb	memory_pool: Deduplicate slab allocation code (#28)	2016-09-07 13:20:42 +01:00
Merry	d646c3119d	Merge pull request #29 from lioncash/list ... intrusive_list: Minor changes	2016-09-07 12:10:05 +01:00
Mat M	6a2174ebfa	Add missing explicit specifiers (#27)	2016-09-07 12:08:48 +01:00
Mat M	6e0f27a500	types: Add helpers for determining single and doubleword extension registers (#26)	2016-09-07 12:08:35 +01:00
Lioncash	c052f9f84c	intrusive_list: Amend doxygen parameter documentation	2016-09-06 22:54:33 -04:00
Lioncash	1c4868ccce	intrusive_list: Correct unused variable	2016-09-06 22:54:25 -04:00
Lioncash	8fb857f9da	intrusive_list: Specify noexcept on swap implementations ... Necessary to fully satisfy the Swappable concept.	2016-09-06 22:47:55 -04:00
Mat M	5bc9ce544f	arm_types: Move into arm folder (#25)	2016-09-06 00:52:33 +01:00
Mat M	b40d19c3b7	location_descriptor: Provide operator<< string overload (#24)	2016-09-05 21:31:25 +01:00
MerryMage	1f61a3d7bc	jitstate: Rename fields s/guest_FPSCR/FPSCR/	2016-09-05 14:42:21 +01:00
Mat M	6d53bb6d7e	arm_types: Split out LocationDescriptor (#20) ... This isn't really an ARM-specific type, since it's used to indicate a Block location.	2016-09-05 11:54:09 +01:00
Mat M	84336cf29d	value: Change Value into a class (#19) ... 'struct' is a little bit of a misnomer, considering it has invariants	2016-09-05 11:53:56 +01:00
Mat M	858796a029	Eliminate variable shadowing warnings with MSVC (#17)	2016-09-04 11:30:57 +01:00
Mat M	7f9a0c3c38	Remove unnecessary explicit includes (#16)	2016-09-03 21:48:03 +01:00
Mat M	26db11cd71	reg_alloc: Use a strongly-typed enum for representing OpArg type (#15)	2016-09-03 18:30:03 +01:00
Mat M	05b189bc26	arm_types: Specialize std::hash for LocationDescriptor (#14) ... Same thing, but with the benefit of working with anything that uses std::hash by default.	2016-09-03 12:48:47 +01:00
Mat M	8c4df46580	FPSCR: Make value constructor explicit (#13) ... Maintains consistency between the PSR helper.	2016-09-03 12:48:31 +01:00
Mat M	3e03524658	assert: Use attribute specifier syntax with non MSVC compilers (#12)	2016-09-03 12:48:07 +01:00
MerryMage	cc3e7e71aa	bit_util: std::bitset-based BitCount implementation ... Suggestion by @lioncash.	2016-09-02 22:00:48 +01:00
Mat M	5aa4f753b6	load_store: Add checks for unpredictability to other singular store instructions (#11)	2016-09-02 21:10:28 +01:00
MerryMage	e8764c129f	bit_util: Implement BitCount portably	2016-09-02 19:05:49 +01:00
Mat M	6ec651498d	arm: Add PSR helper type (#3)	2016-09-02 17:34:33 +01:00
Mat M	00d0f4d5ff	load_store: Add correctness checks for STRD variants (#7) ... STRD doesn't allow the use of the PC in either Rt or Rt2	2016-09-02 17:32:02 +01:00
Mat M	d16badbc04	get_set_elimination_pass: Replace decltype with direct type retrieval (#9)	2016-09-02 17:30:21 +01:00
Mat M	1e781d911a	reg_alloc: const correctness (#8)	2016-09-02 17:30:01 +01:00
MerryMage	ba04be5071	travis: Build on OS X	2016-09-02 17:08:09 +01:00
MerryMage	b3743e9453	Revert "arm_types: Don't use std::hash<u64>() for LocationDescriptorHash" ... This reverts commit 519c714dbc.	2016-09-02 14:33:56 +01:00
MerryMage	519c714dbc	arm_types: Don't use std::hash<u64>() for LocationDescriptorHash ... Apple Clang (clang-600.0.54 on x86_64-apple-darwin13.4.0) complains with: implicit instantiation of undefined template 'std::__1::hash<unsigned long long>'	2016-09-02 12:45:09 +01:00
Mat M	a465b2ddbc	ir_emitter: Fix typo. ClearExlcusive -> ClearExclusive (#5)	2016-09-02 12:17:22 +01:00
Mat M	ea157dfd52	translate_arm: const-correctness (#6)	2016-09-02 12:17:02 +01:00
MerryMage	711b3e29d3	interface: Allow ClearCache to be called at any time	2016-09-02 10:59:33 +01:00
Mat M	fb6d838bd9	dynarmic: Remove poison_memory ClearCache parameter (#1) ... Unused since the switch to Xbyak	2016-09-01 09:47:09 +01:00
Mat M	7e3c981974	translate: Forward declare LocationDescriptor (#2)	2016-09-01 09:46:35 +01:00
MerryMage	4321e829d1	callbacks: Add user_arg argument to InterpreterFallback	2016-09-01 02:00:08 +01:00
MerryMage	3b5c43b427	Optimization: Read page-table directly for memory access	2016-09-01 00:58:02 +01:00
MerryMage	57169ec093	abi: Implement ABI_PushCallerSaveRegistersAndAdjustStack and ABI_PopCallerSaveRegistersAndAdjustStack	2016-09-01 00:57:22 +01:00
MerryMage	702e181b35	backend_x64/abi: Reversing XMM list leads to incorrect ordering	2016-08-31 23:06:49 +01:00
MerryMage	b10c438e8e	jitstate: Remove code argument from ResetRSB	2016-08-31 21:57:33 +01:00
Lioncash	ea6a4e82b5	block_of_code: Make CallFunction accept function pointers only	2016-08-31 21:51:44 +01:00
Lioncash	37d64f0c86	hostloc: Simplify static_assert	2016-08-28 22:10:23 +01:00
Lioncash	f2bf795876	intrusive_list: Interface changes ... - Remove the root pointer from iterators. This is unnecessary, since the only way to get a valid iterator is either from a node itself (it transiently becomes an iterator via the underlying interface), or through the iterator interface for the list. This should also result in better code generation, as each increment or decrement of an iterator is now branchless. - Remove iterator_to This is actually a pretty dangerous function, since it would immediately create an iterator into the list using the given item, even if it's not actually part of the list. This was only left around due to lack of type handling around constructors. - Add other overloads for erase() and remove() Now handles iterators, pointers, and references.	2016-08-28 20:56:40 +01:00
MerryMage	7912a79fa5	emit_x64: align before emitting blocks	2016-08-27 11:04:43 +01:00
MerryMage	41c8dabf0b	block_of_code: nop should probably default to a size of 1	2016-08-27 10:57:48 +01:00
MerryMage	dca3b2f079	Implement VMRS and VMSR	2016-08-26 22:47:54 +01:00
MerryMage	814348371e	emit_x64: EmitX64::Emit: block.Location() returns by value	2016-08-26 19:43:29 +01:00
Lioncash	79545661b3	intrusive_list: De-duplicate some iterator code ... These increment/decrement variants can just leverage the other overloads.	2016-08-26 19:15:11 +01:00
MerryMage	4f6ea715b2	emit_x64: EmitX64::Emit doesn't need descriptor argument	2016-08-26 19:14:25 +01:00
Lioncash	32c24d2cb3	Use 'false' instead of '0' in asserts	2016-08-26 18:52:08 +01:00
MerryMage	ba31f43672	reg_alloc: UseDefOpArgXmm: default value for argument desired_location should be any_xmm, not any_gpr	2016-08-26 18:50:08 +01:00
MerryMage	7fedf04e79	reg_alloc: Deduplicate constants in RegAlloc::HostCall that were already defined by abi.h	2016-08-26 18:43:50 +01:00
MerryMage	59a8e14d1c	reg_alloc: Correct OpArg::setBit for Reg	2016-08-26 15:23:38 +01:00
MerryMage	065c53ebfc	emit_x64: Make ZeroIfNaN64 branchless	2016-08-26 15:23:08 +01:00
MerryMage	9901ed0f51	block_of_code: Optimize nops	2016-08-26 13:46:19 +01:00
Lioncash	0102951bdd	Convert formatting over to fmtlib	2016-08-26 13:13:19 +01:00
Lioncash	ee4b30eee4	externals: Add fmt as a submodule	2016-08-26 13:13:19 +01:00
MerryMage	ed3a686d1d	Implement public header files	2016-08-26 00:44:50 +01:00
MerryMage	656d4f7252	emit_x64: inhibit_emission is obsolete ... Not used anymore; unused ever since intrusive lists were introduced.	2016-08-25 23:24:16 +01:00
MerryMage	4322c0907c	microinstruction: Rename FindUseWithOpcode to GetAssociatedPseudoOperation, encapsulate associated variables	2016-08-25 21:08:47 +01:00
MerryMage	30df51c2dc	ir_emitter: Should be in the IR namespace, not the Arm namespace	2016-08-25 17:36:42 +01:00
MerryMage	922d1fd198	Merge branch 'xbyak'	2016-08-25 16:54:48 +01:00
MerryMage	d04b9eaa81	backend_x64/block_of_code: Reset labels when ClearCache() is called	2016-08-25 16:18:18 +01:00
MerryMage	e32812cd00	Port x64 backend to xbyak	2016-08-25 16:18:17 +01:00
Lioncash	0e12fb6a56	basic_block: Move all variables behind a public interface	2016-08-25 16:14:37 +01:00
Lioncash	1d8432487d	arm_types: Provide the not-equals operator overload for LocationDescriptor ... Generally if == has an overload, != should be provided for symmetry.	2016-08-25 14:08:16 +01:00
MerryMage	13908c5a58	reg_alloc: Insert braces around DEBUG_ASSERT ... DEBUG_ASSERT becomes an empty statement in release-mode; an if statement with an empty statement produces a compiler warning.	2016-08-25 13:09:18 +01:00
MerryMage	dc26afbd7e	translate_arm: Translate more than one conditional instruction in a block	2016-08-25 13:05:33 +01:00
MerryMage	aa9b63bac4	basic_block: DumpBlock now dumps terminal details	2016-08-25 13:01:32 +01:00
Lioncash	1395baefa9	interface: Return register files by const reference ... Prevents unnecessary copies where they aren't particularly required.	2016-08-25 12:51:41 +01:00
Lioncash	37755cbfec	translate: Simplify function pointer calls ... They can just be called like regular functions	2016-08-24 23:19:50 +01:00
Lioncash	9b874c2e23	CMakeLists: Add FPSCR.h to the list of headers ... Whoops, that one's on me	2016-08-24 23:19:49 +01:00
MerryMage	22cca5ff72	emit_x64: Actually advance RSB pointer	2016-08-24 23:19:47 +01:00
Lioncash	eba3a06d80	frontend: Introduce FPSCR register helper class ... Encapsulates all of the FPSCR state.	2016-08-24 20:51:14 +01:00
MerryMage	b5a86889cd	Implement VCVT	2016-08-23 22:20:04 +01:00
MerryMage	445aad0639	x64/emitter: Add opBits argument to CVTSI2SS and CVTSI2SD	2016-08-23 21:58:34 +01:00
MerryMage	78464a8f01	translate_arm/vfp2: Implement VSTM (A1, A2)	2016-08-23 20:54:38 +01:00
MerryMage	a96704eb0f	arm_types: new_reg >= 0 is always true since new_reg is unsigned	2016-08-23 20:11:41 +01:00
MerryMage	7a01dba3c4	arm_types: Change type signature of operator+ to size_t instead of int	2016-08-23 20:07:53 +01:00
MerryMage	af9a68f0d1	translate_arm/vfp2: Implement VLDM (A1, A2)	2016-08-23 20:07:06 +01:00
Lioncash	d5805cc6eb	intrusive_list: Add size querying ... Since we store pointers and have an interface for iterators set up, the count is just the distance from the beginning to the end of the list. Nice thing is that because of this, basic blocks also get the ability to have a size count without needing to do anything directly.	2016-08-23 19:52:09 +01:00
Lioncash	2180a4be7a	basic_block: Use a range-based for loop for iteration	2016-08-23 19:51:01 +01:00
Lioncash	897b776250	string_util: Use C++ attribute specifier for format strings ... This is also compatible with both clang and GCC	2016-08-23 19:38:48 +01:00
Lioncash	867d345fdc	disassembler: Deduplicate SignStr ... Also just makes it return a character, rather than a pointer to a string.	2016-08-23 16:40:33 +01:00
Lioncash	8bed891011	x64 emitter: Fix swapped parameter names	2016-08-23 16:39:38 +01:00
MerryMage	c8b2f63c93	get_set_elimination_pass: Eliminate unnecessary gets/sets of extended registers	2016-08-23 15:57:20 +01:00
MerryMage	e0f9dead5d	microinstruction: Identity's type depends on the type of its argument	2016-08-23 15:48:30 +01:00
Lioncash	67706c208b	assert: Use false in asserts rather than 0 ... Quiets extended warnings.	2016-08-23 14:31:54 +01:00
MerryMage	8c7a81a308	VPOP and VPUSH are floating-point load-store instructions	2016-08-23 14:26:50 +01:00
MerryMage	34cffa86a4	dead_code_elimination_pass: Update to use IR::Inst::MayHaveSideEffects	2016-08-23 13:12:14 +01:00
Lioncash	46573eb538	intrusive_list: Add insert_before() and insert_after() helper functions ... Small helpers for inserting nodes before and after an existing one. insert() is the same as insert_before(), so insert() is just made to be an alias of this.	2016-08-23 12:38:57 +01:00
MerryMage	8d1b9f32ca	Standardize indentation of switch statments	2016-08-23 12:19:27 +01:00
MerryMage	2471be317e	arm_types: Implement LocationDescription::FPSCR_RMode	2016-08-23 02:22:04 +01:00
Lioncash	47f285249b	microinstruction: Introduce convenience informational functions ... Whenever more rigorous optimizations are attempted (or even basic ones), it's usually helpful to know what overall kind of instruction is being dealt with, in the event certain classes of instructions may be eligible for optimization.	2016-08-22 21:36:48 +01:00
Lioncash	06ec4b5977	microinstruction: Make constructor explicit	2016-08-22 16:01:18 +01:00
Lioncash	1bedd3bd7f	CMakeLists: Clean up ... Moves functions out of the main CMakeLists file into module files that can just be included whenever necessary. This also uses the CMake provided variables for enforcing compiler requirements.	2016-08-22 15:55:39 +01:00
MerryMage	72250b119f	backend_x64/block_of_code: Add more floating point constants ... * MFloatPositiveZero32 * MFloatPositiveZero64 * MFloatMinS32 * MFloatMaxS32 * MFloatMinU32 * MFloatMaxU32	2016-08-22 15:54:19 +01:00
MerryMage	a32689c832	x64/emitter: Implement CMPxxSD instructions	2016-08-22 15:54:18 +01:00
MerryMage	843d29b5a9	translate_arm/branch: Read-after-write in arm_BLX_reg ... When BLX LR is translated, BXWritePC(GetRegister(Reg::LR)) was executed after the SetRegister(Reg::LR, _) update was done.	2016-08-22 15:53:56 +01:00
MerryMage	d8bee60947	translate_thumb: Read-after-write in thumb16_BLX_reg ... When the instruction BLX LR is translated, BXWritePC(GetRegister(Reg::LR)) was executed after the SetRegister(Reg::LR, _) update was performed.	2016-08-22 14:28:51 +01:00
Lioncash	1abe881921	basic_block: Add proxy member functions for the instruction list ... Currently basic block kind of acts like a 'dumb struct' which makes things a little more verbose to write (as opposed to keeping it all in one place, I guess). It's also a little wonky conceptually, considering a block is composed of instructions (i.e. 'contains' them). So providing accessors that make it act more like a container can make working with algorithms a little nicer. It also makes the API a little more defined. Ideally, the list would be only available through a function, but currently, the pool allocator is exposed, which seems somewhat odd, considering the block itself should manage its overall allocations (with placement new, and regular new), rather than putting that sanitizing directly on the IR emitter (it should just care about emission, not block state). However, recontaining that can be followed up with, as it's very trivial to do.	2016-08-22 13:44:56 +01:00
Lioncash	226d66dd5b	intrusive_list: satisfy the Swappable concept	2016-08-22 12:38:16 +01:00
Lioncash	2a9fdacc60	intrusive_list: move iterator implementation above list ... Will make keeping non-member list functions easier to keep together with the class.	2016-08-22 12:38:16 +01:00
Lioncash	669ffb5f3a	intrusive_list: Add pop_back(), pop_front(), front(), and back() member functions	2016-08-20 21:26:16 +01:00
Lioncash	86f803da04	reg_alloc: Use Inst's HasUses() function where applicable	2016-08-20 21:26:09 +01:00
Lioncash	a8ba15f0d5	intrusive_list: Make Remove and IsEmpty stdlib compatible ... Makes the name match the standard library equivalents. C++17 introduces non-member empty() which allows for nicer handling in generic contexts. May as well make the data structure compatible with it.	2016-08-19 20:25:18 +01:00
Lioncash	23d190f7b0	intrusive_list: Support inserters ... Allows std::inserter, std::back_inserter, and std::front_inserter to work with intrusive lists.	2016-08-19 20:25:17 +01:00
Lioncash	36a0ad5bc2	reg_alloc: const correctness for ValueLocation()	2016-08-19 19:33:57 +01:00
MerryMage	2d6a86e43c	Remove <cassert>	2016-08-19 01:53:24 +01:00
MerryMage	192a0029be	ir/opcodes: Implement IR::AreTypesCompatible ... Type-checking is now occuring in more than one place.	2016-08-19 01:34:14 +01:00
Tillmann Karras	9782e7da3f	verification_pass: show type errors	2016-08-19 01:17:30 +01:00
Tillmann Karras	dad7724b86	TranlateArm: implement remaining multiplies ... SMLALxy, SMLAxy, SMULxy SMLAWy, SMULWy, SMLAD, SMLALD, SMLSD, SMLSLD, SMUAD, SMUSD	2016-08-19 01:08:38 +01:00
MerryMage	fe15cbd50e	translate_arm/parallel: Detect UNPREDICTABLE instructions	2016-08-19 00:59:07 +01:00
MerryMage	2119dfc926	translate_arm/multiply: MLA is UNPREDICTABLE when Ra == R15	2016-08-19 00:59:05 +01:00
MerryMage	0d0f4b1b4f	translate_arm/load_store: Correct implementation for LDM*	2016-08-19 00:59:04 +01:00
MerryMage	4acc481463	translate_arm/load_store: Handle unpredictable instructions ... This necessated handling literal versions of the instructions separately as they had different requirements. The rationale for detecting unpredictable instructions is because: a. they are unlikely to be outputted by a well-behaved compiler b. their behaviour may change between different processors I would rather unpredictable instructions fail loudly than silently do approximately the right thing.	2016-08-19 00:59:02 +01:00
MerryMage	5869e79b9c	translate_arm: Simplify EmitImmShift and EmitRegShift	2016-08-19 00:21:31 +01:00
Lioncash	fe9329ef3e	intrusive_list: Add list class type definitions; extend iterator interface ... Adds type definitions, and extends the list interface to support all standard library forms of iterator creation.	2016-08-18 23:47:26 +01:00
Lioncash	95a83543f2	intrusive_list: Get rid of unnecessary static_casts ... The only valid objects to add to the list are those that inherit from IntrusiveListNode. Therefore anything being added to the list that isn't inheriting from it will cause compilation to fail.	2016-08-18 23:47:26 +01:00
Lioncash	67509935f6	intrusive_list: Eliminate need for separate const iterator construct ... This generalizes the regular iterator to be compatible with both use cases. Passing in the list instance directly isn't needed, because the only way you'd ever get a valid instantiation of an iterator is from a list instance itself.	2016-08-18 23:47:26 +01:00
MerryMage	b8cf43c43e	translate_arm/data_processing: Rd == R15 is unpredictable for rsr instructions	2016-08-18 18:23:05 +01:00
MerryMage	efc8d2f772	arm_translator: NV conditional is obsolete	2016-08-18 18:21:48 +01:00
MerryMage	5f7d940fde	disassemble_arm: Partially implement coprocessor and hint instructions	2016-08-18 18:21:16 +01:00
MerryMage	36a916a766	decoder/arm: Correct NOP decoder	2016-08-18 18:20:29 +01:00
MerryMage	e9e7ac6e65	decoder/arm: Correct PLD decoder for v6K	2016-08-18 18:19:34 +01:00
MerryMage	269160ef0d	emit_x64: Clear RSB-related caches when ClearCache() is called	2016-08-18 18:18:44 +01:00
MerryMage	1a3f3ac435	emit_x64: Correct behaviour of PackedOperation for immediate argument ... x64 MOVD_xmm does not support an immediate oparg	2016-08-18 18:17:17 +01:00
MerryMage	b2de47954b	EmitX64: Emit correct cycle count on cond failure	2016-08-18 18:16:18 +01:00
Lioncash	841098a0bc	ir: separate components out a little more	2016-08-17 20:46:21 +01:00
Lioncash	9690d1423d	intrusive_list: explicitly default relevant constructors	2016-08-17 20:46:11 +01:00
Lioncash	cbd99e4367	jitstate: Use std::array's fill() in ResetRSB ... Performs the equivalent behavior	2016-08-17 10:10:43 +01:00
Lioncash	74ee92ee38	jitstate: const correctness ... GetReturnFromRunCodeAddress is const qualified, so this can accept a const pointer. This also allows for making the constructor accept a const pointer as well.	2016-08-17 10:10:43 +01:00
Lioncash	9ed9f4c565	mp: Generalize function information retrieval ... Generalizes MemFnInfo to be compatible with all function types. Also adds type introspection for arguments, as well as helper templates for the common types supported by all partial specializations.	2016-08-17 10:08:40 +01:00
Lioncash	439619c827	reg_alloc: Make GetRegLoc return by const reference ... Considering a HostLocInfo instance houses a std::vector, every time this function is called can cause a potential heap allocation. This can be somewhat unnecessary because this function is only used to query for information we already have. Considering this is used by several other internal query functions such as IsRegisterOccupied, IsRegisterAllocated, and IsLastUse, this will result in better codegen (returning an address is just 3 instructions excluding the ret instruction for returning, meanwhile heap alloc can be 60+). This also renames the function to have the same name as its non-const counterpart, since overloading will just select the correct function instead of putting that onus on the developer.	2016-08-17 10:08:08 +01:00
MerryMage	0ebb572e2d	Optimization: Make RSB a ring buffer instead of a stack	2016-08-15 15:48:22 +01:00
MerryMage	7d7ac0af71	Optimization: Make SVC use RSB	2016-08-15 15:02:08 +01:00
MerryMage	6c45619aa1	Optimization: Implement terminal LinkBlockFast	2016-08-15 14:33:17 +01:00
MerryMage	624e84fa09	Optimization: Tweak RSB	2016-08-15 14:08:06 +01:00
MerryMage	070298b948	Optimization: bugfix! Return Stack Buffer location hash calculation was incorrect	2016-08-15 13:21:58 +01:00
MerryMage	e164ede4dc	TranslateArm: Implement MRS, MSR (imm), MSR (reg)	2016-08-15 11:50:49 +01:00
bunnei	30f3d869cc	TranslateArm: Implement VPUSH and VPOP.	2016-08-13 19:37:03 +01:00
MerryMage	9c82a12f8f	ir_opt: Update VerificationPass to current IR	2016-08-13 18:39:49 +01:00
MerryMage	8fc21f481a	RegAlloc: Handle case when def is unused	2016-08-13 01:55:03 +01:00
MerryMage	d43d97b990	EmitX64/EmitPushRSB: Assert that patch location is of correct size	2016-08-13 00:52:31 +01:00
MerryMage	960d14d18e	Optimization: Implement Return Stack Buffer	2016-08-13 00:10:23 +01:00
bunnei	8e68e6fdd9	TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.	2016-08-12 19:00:44 +01:00
bunnei	4b09c0d032	TranslateArm: Implement QADD8 and UQADD8.	2016-08-12 19:00:44 +01:00
bunnei	127fbe99cb	TranslateArm: Implement QSUB8.	2016-08-12 19:00:44 +01:00
bunnei	86fe29c6d2	TranslateArm: Implement UQSUB8.	2016-08-12 19:00:44 +01:00
MerryMage	1029fd27ce	Update documentation (2016-08-12)	2016-08-12 18:17:31 +01:00
MerryMage	3808938c98	Fix SETEND	2016-08-11 19:15:58 +01:00
bunnei	218980cf69	load_store: Implement LDRSB and LDRSH.	2016-08-11 17:18:20 +01:00
MerryMage	0e5593ba62	TranslateArm: Implement SETEND	2016-08-11 17:15:33 +01:00
MerryMage	8964b38cf9	IR/DumpBlock: Print references to ExtRegs	2016-08-11 17:15:02 +01:00
MerryMage	b4c586d5ef	TranslateArm: VSTR: Correct behaviour in big-endian mode	2016-08-10 16:43:37 +01:00
MerryMage	945498a16a	DisassemblerArm: Disassemble SETEND	2016-08-10 16:15:07 +01:00
bunnei	8e8db6e137	TranslateArm: Implement VSTR.	2016-08-10 15:01:23 +01:00
MerryMage	df39308e03	TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB	2016-08-09 22:57:20 +01:00
MerryMage	d921390928	TranslateArm: Add santity check to see if we've emitted a terminal instruction	2016-08-09 22:47:41 +01:00
MerryMage	2eec43178a	IR: Opaque can be of any type	2016-08-09 22:46:44 +01:00
MerryMage	29d30bf931	Interface: Added Jit::Reset to reset CPU state	2016-08-09 22:45:54 +01:00
MerryMage	82f42d065f	DisassemblerArm: Implemented disassembly of STR*/LDR* instructions	2016-08-09 22:44:42 +01:00
MerryMage	d0d51ba346	TranslateArm: Implement STM, STMDA, STMDB, STMIB	2016-08-08 22:49:11 +01:00
Tillmann Karras	5d26899ac9	Add simplified LogicalShiftRight64 IR opcode	2016-08-08 22:27:05 +01:00
Tillmann Karras	ccb2aa96a5	Add support for the APSR.Q flag	2016-08-08 22:27:04 +01:00
Tillmann Karras	11e0688e5f	Fix build on case-sensitive file systems	2016-08-08 22:27:03 +01:00
MerryMage	85549d7ae2	TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB	2016-08-08 22:26:06 +01:00
MerryMage	46e4864707	ArmTypes: Add RegListToString and reorganise	2016-08-08 22:20:28 +01:00
MerryMage	975f011fc0	BackendX64/RegAlloc: Do not allocate RSP for guest use	2016-08-08 16:01:07 +01:00
MerryMage	abd113f160	EmitX64: Renamed patch_jmp_locations to patch_jg_locations	2016-08-08 15:56:07 +01:00
MerryMage	52fa998e6b	EmitX64: EmitTerminalLinkBlock: Fix behaviour when setting T and E flags	2016-08-07 22:47:43 +01:00
MerryMage	04c1a0d2de	EmitX64: Switch MXCSR when switching to interpreter	2016-08-07 22:47:17 +01:00
MerryMage	edb236ab07	Correct implementation of thumb16_SVC and arm_SVC	2016-08-07 22:19:39 +01:00
MerryMage	a32063fa60	EmitX64: Implement block linking	2016-08-07 22:11:39 +01:00
MerryMage	328422b740	RegAlloc: HostCall flushes all XMM regsiters	2016-08-07 21:02:16 +01:00
MerryMage	4dcd1d1859	Arm: BLX is UNPREDICTABLE when Rm is PC	2016-08-07 20:50:33 +01:00
MerryMage	1af5bef32c	TranslateArm: Implement BLX (imm), BLX (reg) and BXJ	2016-08-07 20:40:31 +01:00
MerryMage	939bb5c0cb	TranslateArm: Implement NOP	2016-08-07 20:08:31 +01:00
MerryMage	e48df9d8fd	TranslateArm: Implement Hint instructions as NOPs	2016-08-07 20:04:48 +01:00
MerryMage	3a465ba4a8	VFP: Implement VLDR	2016-08-07 19:59:35 +01:00
MerryMage	a2c2db277b	VFP: Implement VMOV (all variants)	2016-08-07 19:25:12 +01:00
MerryMage	aba705f6b9	BackendX64: Merge Routines into BlockOfCode	2016-08-07 18:08:48 +01:00
MerryMage	0f412247ed	VFP: Implement VSQRT	2016-08-07 12:19:07 +01:00
MerryMage	cd8e7c0504	VFP: Implement VNEG	2016-08-07 12:04:21 +01:00
MerryMage	da33af5abe	VFP: Implement VMLA, VMLS, VNMLA, VNMLS	2016-08-07 11:49:06 +01:00
MerryMage	3f1345a1a5	VFP: Implement VNMUL, VDIV	2016-08-07 10:56:12 +01:00
MerryMage	12e7f2c359	VFP: Implement VMUL	2016-08-07 10:21:14 +01:00
MerryMage	97b5fa173f	VFP: Implement VSUB	2016-08-07 01:45:52 +01:00
MerryMage	ce6b5f8210	VFP: Implement VABS	2016-08-07 01:27:18 +01:00
MerryMage	f88b1b4c2e	FPSCR: Save and restore MSCSR across supervisor call, fix MXCSR exception mask	2016-08-07 01:10:19 +01:00
MerryMage	c35f06470f	VFP: Interpret VFP instructions when FPSCR.Len or FPSCR.Stride != 1	2016-08-06 23:01:18 +01:00
MerryMage	94b99f5949	Common: Add an intrusive list implementation; remove use of boost::intrusive::list.	2016-08-06 22:23:01 +01:00
Tillmann Karras	9264e2e04c	Use XOR when loading a zero immediate	2016-08-06 21:17:11 +01:00
Tillmann Karras	55204a80d0	Implement SMMLA, SMMLS, SMMUL	2016-08-06 21:17:11 +01:00
Tillmann Karras	846d07d7b5	Add Sub64 opcode	2016-08-06 21:17:11 +01:00
Tillmann Karras	b9f4f1ed0f	Add carry support to MostSignificantWord	2016-08-06 21:17:11 +01:00
Tillmann Karras	01aebcb385	Remove *MulHi wrappers	2016-08-06 21:17:11 +01:00
Tillmann Karras	5e047107a0	Disassemble more instructions ... CLZ, SEL, USAD8, USADA8, SSAT, SSAT16, USAT, USAT16, SMLAL*, SMLA*, SMUL*, SMLAW*, SMULW*, SMLAD, SMLALD, SMLSD, SMLSLD, SMUAD, SMUSD	2016-08-06 21:17:11 +01:00
Tillmann Karras	f99cb613cf	Disassemble packs and more multiplies	2016-08-06 21:17:11 +01:00
MerryMage	7915f97d98	TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning)	2016-08-06 20:42:06 +01:00
MerryMage	4d127c19dd	Common: Add a memory pool implementation, remove use of boost::pool	2016-08-06 20:41:00 +01:00
MerryMage	411e804b0d	Interface: Forward declare Arm::LocationDescriptor	2016-08-06 20:11:35 +01:00
MerryMage	4b31ea25a7	VFP: Implement VADD.{F32,F64}	2016-08-06 20:03:15 +01:00
MerryMage	8ff414ee0e	Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top.	2016-08-06 20:03:15 +01:00
MerryMage	94d5738f62	BackendX64/Routines: Add floating-point constants	2016-08-06 20:01:47 +01:00
MerryMage	8754728a82	BackendX64/RegAlloc: Corrected code emitted by EmitMove for XMM->Spill case	2016-08-06 20:01:47 +01:00
MerryMage	8cc4fe8a10	BackendX64/RegAlloc: HostLocToX64 now handles XMM registers properly	2016-08-06 20:01:47 +01:00
bunnei	2448d52394	load_store: Use correct types for LDR/STR.	2016-08-05 20:51:32 -04:00
bunnei	8c2300d477	arm: Implement LDRD reg/imm instructions.	2016-08-05 20:05:02 -04:00
bunnei	72608b7af6	arm: Handle Cond::NV (some 3DS games use this despite being obsolete).	2016-08-05 20:05:02 -04:00
bunnei	ec3a98cf95	arm: Implement LDRH reg/imm instructions.	2016-08-05 20:05:01 -04:00
bunnei	192a0fba7a	arm: Implement LDRB reg/imm instructions.	2016-08-05 20:05:00 -04:00
bunnei	dfb318f208	arm: Implement STRD reg/imm instructions.	2016-08-05 20:04:59 -04:00
bunnei	e931dc2496	arm: Implement STRH reg/imm instructions.	2016-08-05 20:04:58 -04:00
bunnei	9f77662b24	arm: Implement STRB reg/imm instructions.	2016-08-05 20:04:57 -04:00
bunnei	caab1bbc7c	arm: Implement STR reg/imm instructions.	2016-08-05 20:04:56 -04:00
bunnei	b09ecb4532	arm: Implement LDR reg/imm instructions.	2016-08-05 20:04:55 -04:00
MerryMage	856298577d	EmitX64: Don't give MOVSX or MOVZX an immediate oparg	2016-08-06 01:03:39 +01:00
MerryMage	640ce48baa	VFP: Implement {Get,Set}ExtendedRegister{32,64}	2016-08-05 19:06:10 +01:00
MerryMage	d31bbd6d14	Common/x64/CpuDetect: Disable MSVC warning for strncpy	2016-08-05 18:44:01 +01:00
MerryMage	4c0a85f3b3	EmitX64: Correct EmitPack2x32To1x64 implementation	2016-08-05 18:43:24 +01:00
MerryMage	742eeb8913	BackendX64/RegAlloc: Correct debugging asserts and correct UseDef behaviour for spill locations	2016-08-05 18:43:22 +01:00
MerryMage	d2aeb56503	Common: DEBUG_ASSERTs weren't enabled	2016-08-05 18:43:21 +01:00
MerryMage	d80dcc5367	BackendX64/EmitX64: Eliminate unnecessary MOVs in Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong, Pack2x32To1x64	2016-08-05 15:27:29 +01:00
MerryMage	2b025183a2	BackendX64/RegAlloc: Correct UseDefRegsiter behaviour for last use	2016-08-05 15:24:25 +01:00
MerryMage	b4aa01ccf4	Merge remote-tracking branch 'tilkax/master'	2016-08-05 14:14:06 +01:00
MerryMage	94e75ad32f	BackendX64/EmitX64: Reduce number of MOVs by using reg_alloc.{RegisterAddDef,UseDefOpArg,UseOpArg}	2016-08-05 14:11:27 +01:00
MerryMage	92bd5f214b	BackendX64/RegAlloc: Add RegisterAddDef, UseDefOpArg, UseOpArg	2016-08-05 14:10:39 +01:00
MerryMage	01cfaf0286	IR: Properly support Identity in IR::Value	2016-08-05 14:09:10 +01:00
MerryMage	ca40015145	IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)	2016-08-05 14:07:27 +01:00
Tillmann Karras	fce8c86c90	Implement RSB ... somehow missed this earlier	2016-08-05 02:13:26 +01:00
Tillmann Karras	eb2e6e8bea	Implement some multiplies	2016-08-05 02:09:54 +01:00
Tillmann Karras	72c503016c	Fix Pack2x32To1x64 ... Not sure how to fix this properly.	2016-08-05 02:09:30 +01:00
Tillmann Karras	3fdc093d10	Add more IR opcodes for multiply instructions ... Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64, Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong	2016-08-05 02:09:30 +01:00
Tillmann Karras	af27ef8d6c	Optionally disassemble x86_64 code using LLVM	2016-08-05 02:08:41 +01:00
bunnei	691e4139fa	arm: Implement B/BL/BX instructions.	2016-08-03 16:49:01 -04:00
Tillmann Karras	fc33f1d374	Implement more instructions ... SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16	2016-08-03 00:47:17 +01:00
Tillmann Karras	30a90295b9	Implement data processing instructions ... ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB, TEQ, TST The code could use some serious deduplication...	2016-08-03 00:47:16 +01:00
Tillmann Karras	fe71cc9d78	Disassemble reg-shifted regs in lower case	2016-08-03 00:47:16 +01:00
Tillmann Karras	2488926341	Add IR opcode RotateRightExtended ... to rotate through the carry flag	2016-08-03 00:47:16 +01:00
Tillmann Karras	306e070ab5	Use opcodes.inc for emit_x64.h	2016-08-03 00:44:08 +01:00
Tillmann Karras	61eddbd1fa	Fix Linux build	2016-08-03 00:44:08 +01:00
MerryMage	1252bd653d	RegAlloc: Define constructors for HostLocInfo to make MSVC happy	2016-08-03 00:25:42 +01:00
MerryMage	a875c0c720	TranslateArm: Stub more ARM instructions	2016-08-02 21:59:33 +01:00
MerryMage	deb5e2c10d	IR::DumpBlock: Incorrect use of std::map::at	2016-08-02 13:47:05 +01:00
MerryMage	4414ec5bc8	RegAlloc: Allow allocation of XMM registers	2016-08-02 13:46:12 +01:00
MerryMage	864081d1a0	BackendX64: ArithmeticShiftRight: Fix incorrect immediate size for SAR	2016-08-02 12:00:11 +01:00
MerryMage	6097a21955	TranslateArm: Reorganisation - Split visitor into multiple .cpp files	2016-08-02 11:54:04 +01:00
MerryMage	93af160c97	arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface	2016-08-02 11:54:02 +01:00
MerryMage	be87038ffd	IROpt: Port get/set elimination pass to current IR	2016-08-02 11:51:05 +01:00
MerryMage	51448aa06d	More Speed	2016-07-22 23:55:00 +01:00
MerryMage	5fbfc6c155	Implement some simple IR optimizations (get/set eliminiation and DCE)	2016-07-21 21:48:45 +01:00
MerryMage	90d317b868	Implement memory endianness. Implement Thumb SETEND instruction.	2016-07-20 15:34:17 +01:00
MerryMage	98bd7ff6a5	Decoder/Thumb16: Remove BL{,X} prefix/suffix decoders. We have 32-bit thumb instruction support.	2016-07-20 12:08:17 +01:00
Merry	95316b8443	Merged in Subv/dynarmic/arm_mem_tests (pull request #4) ... Added some fuzz tests for most cases of ARM Load/Store instructions	2016-07-20 10:19:55 +01:00
MerryMage	95588d3faa	Fix Thumb BLX (imm), BL (imm) for negative immediates	2016-07-18 22:48:23 +01:00
MerryMage	3f11a149d7	Implement Thumb Instructions: BLX (imm), BL (imm)	2016-07-18 22:18:58 +01:00
MerryMage	e0d6e28b67	Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2)	2016-07-18 21:04:39 +01:00
Subv	ccc61472b9	Added format strings for ARM STRBT encodings A1 and A2	2016-07-18 14:20:58 -05:00
Subv	8617bf80a1	Added format strings for ARM LDRBT encodings A1 and A2	2016-07-18 14:18:39 -05:00
Subv	5d5ea9325c	Added format strings for ARM STRT encodings A1 and A2	2016-07-18 14:05:53 -05:00
MerryMage	2363759c62	Implement thumb STM, LDM. Fix thumb POP implementation for P=1.	2016-07-18 20:05:35 +01:00
MerryMage	8a310777a1	backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC	2016-07-18 20:01:48 +01:00
Subv	77761ba032	Added the format strings for LDRT encodings A1 and A2.	2016-07-18 14:01:18 -05:00
MerryMage	14dcb18bbe	Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2)	2016-07-18 18:48:08 +01:00
MerryMage	a605a43ef9	Implement Thumb Instructions: STRH (imm), LDRH (imm)	2016-07-18 18:28:52 +01:00
MerryMage	f9755870bb	Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg)	2016-07-18 18:02:02 +01:00
Merry	3b8790bf29	Merged in Subv/dynarmic/small_opt (pull request #3) ... Pass the current IR::Block by reference to the emitter.	2016-07-18 17:38:12 +01:00
MerryMage	dfef65d98f	Implement thumb POP instruction	2016-07-18 17:37:48 +01:00
Subv	703a46ec99	Pass the current IR::Block by reference to the emitter. ... This avoids calling the copy constructor more times than needed.	2016-07-18 11:27:33 -05:00
MerryMage	f7e3d7b8d2	Implement Thumb PUSH instruction	2016-07-18 15:11:16 +01:00
MerryMage	9109b226af	Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm)	2016-07-18 11:16:12 +01:00
MerryMage	c18a3eeab4	Better MSVC support ... * Avoiding use of templated variables. * Now compling on MSVC with /WX (warnings as errors). * Fixed all MSVC warnings. * Fixed MSVC source_groups.	2016-07-18 10:38:22 +01:00
MerryMage	bf99ddd065	Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic	2016-07-18 10:33:52 +01:00
MerryMage	28a201da16	Implement Thumb ADR instruction	2016-07-18 09:25:33 +01:00
Subv	0cdf5fe751	Implemented ARM REV and REVSH instructions, with tests.	2016-07-17 14:45:42 -05:00
Merry	24aa24b1bc	Merged in Subv/dynarmic (pull request #1) ... Implemented ARM CMP (imm) instruction.	2016-07-17 19:43:49 +01:00
Subv	7f09510945	Implemented ARM CMP (imm) instruction.	2016-07-17 13:29:37 -05:00
MerryMage	3720da4e19	Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}	2016-07-16 19:23:42 +01:00
MerryMage	4b1c27e64f	Implement arm_ADC_imm	2016-07-14 20:02:41 +01:00
MerryMage	63242924fc	Implement thumb16_SVC	2016-07-14 15:01:30 +01:00
MerryMage	181f78f36e	Common: Remove src/common/logging/log.*	2016-07-14 14:55:08 +01:00
MerryMage	07eaf100ba	Reorganise src/frontend: Add subdirectories disassembler and translate	2016-07-14 14:39:43 +01:00
MerryMage	9b2aff166a	Implement arm_SVC	2016-07-14 14:29:46 +01:00
MerryMage	672ffb93d0	frontend/translator: Skeleton for Arm translator	2016-07-14 13:28:20 +01:00
MerryMage	7d7751c157	Allow IR blocks to require a cond for block entry. ... * IR: Add cond, cond_failed. * backend_x64/EmitX64: Implement EmitCondPrelude	2016-07-14 12:52:53 +01:00
MerryMage	4ab4ca58f9	backend_x64/EmitX64: Improve emitted code for non-carry ArithmeticShiftRight	2016-07-14 09:02:27 +01:00
MerryMage	08e848044d	backend_x64: Inline Routines::GenReturnFromRunCode into emitted code	2016-07-12 16:46:27 +01:00
MerryMage	619b451902	clang support	2016-07-12 14:31:43 +01:00
MerryMage	8449deb0bc	MSVC support	2016-07-12 13:28:09 +01:00
MerryMage	44352680c6	s/thumb1/thumb16/g: Thumb16 refers to 16-bit thumb instructions, and Thumb32 to 32-bit ones	2016-07-12 11:09:34 +01:00
MerryMage	6e46e7899a	Translate/Thumb: Fallback to interpreter for Thumb32 instructions	2016-07-12 11:02:45 +01:00
MerryMage	09420d190b	IR: Implement IR microinstructions ALUWritePC and LoadWritePC	2016-07-12 10:58:14 +01:00
MerryMage	f85b86486b	frontend/TranslateArm: Just interpret all ARM instructions	2016-07-12 09:11:35 +01:00
MerryMage	1410221b47	Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg	2016-07-11 23:11:05 +01:00
MerryMage	e7922e4fef	Implement thumb1_LDR_literal, thumb1_LDR_imm_t1	2016-07-11 22:43:53 +01:00
MerryMage	cbcf61a9e6	backend_x64/RegAlloc: Provide convenience function HostCall to save registers necessary as per host ABI	2016-07-11 15:28:10 +01:00
MerryMage	f0f14fa5e8	Implement thumb1_MOV_reg	2016-07-10 13:10:06 +08:00
MerryMage	8920ce79b9	Implement thumb_CMP_reg_t2	2016-07-10 12:23:16 +08:00
MerryMage	ac2fb6b925	Implement thumb1_MVN_reg	2016-07-10 10:49:01 +08:00
MerryMage	d11df9067d	Implement thumb1_BIC_reg	2016-07-10 10:44:45 +08:00
MerryMage	98a64a92b1	Implement thumb1_ORR_reg	2016-07-10 09:06:38 +08:00
MerryMage	3fe46d2c6f	Implement thumb1_CMN_reg	2016-07-10 08:55:56 +08:00
MerryMage	641dbf8eb4	Implement thumb1_CMP_reg	2016-07-10 08:52:28 +08:00
MerryMage	46408267c3	Implement thumb1_RSB_imm	2016-07-10 08:44:07 +08:00
MerryMage	6536ad9618	Implement thumb1_TST_reg	2016-07-10 08:35:58 +08:00
MerryMage	8145b33882	Implemented thumb1_ROR_reg	2016-07-10 08:18:17 +08:00
MerryMage	207cb74dc9	Implement thumb1_SBC_reg	2016-07-09 08:27:41 +08:00
MerryMage	1953e44532	Implement thumb1_ADC_reg	2016-07-08 22:17:39 +08:00
MerryMage	9e9fa62d5f	Implement thumb1_SUB_imm_t2	2016-07-08 21:48:55 +08:00
MerryMage	8c587df8ce	Implement thumb1_ADD_imm_t2	2016-07-08 21:38:43 +08:00
MerryMage	aa72323823	Implement thumb1_CMP_imm	2016-07-08 21:32:01 +08:00
MerryMage	98f300144b	Implement thumb1_MOV_imm	2016-07-08 21:27:27 +08:00
MerryMage	34be20e4d6	Implement thumb1_SUB_imm	2016-07-08 20:57:53 +08:00
MerryMage	a2e40eb922	Implement thumb1_ADD_imm	2016-07-08 19:15:30 +08:00
MerryMage	92142d5a22	Implement thumb1_SUB_reg	2016-07-08 18:49:30 +08:00
MerryMage	df0c324923	Implement thumb1_EOR_reg	2016-07-08 18:14:54 +08:00
MerryMage	8a0511d297	Implement thumb1_AND_reg	2016-07-08 17:44:53 +08:00
MerryMage	5b56fd12aa	Fix bug: Correct disassembly of thumb1_LSL_reg, thumb1_LSR_reg, thumb1_ASR_reg	2016-07-08 17:44:52 +08:00
MerryMage	d0b48bfb59	Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2	2016-07-08 17:44:51 +08:00
MerryMage	e93fb0ba2b	EmitX64: remove emit_fns map, use a switch statement instead	2016-07-08 15:28:56 +08:00
MerryMage	421ab344ad	EmitX64::EmitTerminalInterpret: Restore RSP before CALL	2016-07-07 22:03:45 +08:00
MerryMage	e5f6450a24	Start implementing Thumb disassembler	2016-07-07 21:51:47 +08:00
MerryMage	f31b530703	Fuzz thumb instructions	2016-07-07 19:01:47 +08:00
MerryMage	5711e62419	Implement terminal instructions	2016-07-07 17:53:09 +08:00
MerryMage	14388ea690	Proper implementation of Arm::Translate	2016-07-04 21:37:50 +08:00
MerryMage	d743adf518	Reorganisation, Import Skyeye, This is a mess	2016-07-04 17:22:11 +08:00
MerryMage	be1c1de552	Common: Add scope_exit.h	2016-07-04 14:56:41 +08:00
MerryMage	6a37072865	Tidy up CMakeLists.txt	2016-07-01 21:23:39 +08:00
MerryMage	2be0639308	Removed daggen	2016-07-01 21:23:22 +08:00
MerryMage	65df15633d	First Commit	2016-07-01 21:01:06 +08:00