MerryMage
3415828fb4
IR: Simplify FP{Single,Double}ToFixed{U,S}{32,64}
2020-04-22 20:53:46 +01:00
Lioncash
e30f9816ec
A32/decoder: Add missing <algorithm> includes
...
These includes should be present, as we use std::find_if() within these headers.
2020-04-22 20:53:46 +01:00
Lioncash
4507627905
emit_x64_vector: Provide AVX path for EmitVectorMinU64()
2020-04-22 20:53:46 +01:00
Lioncash
fd49a62b06
emit_x64_vector: Provide AVX path for EmitVectorMinS64()
2020-04-22 20:53:46 +01:00
Lioncash
770723f449
emit_x64_vector: Provide AVX path for EmitVectorMaxU64()
2020-04-22 20:53:46 +01:00
Lioncash
8fb90c0cf1
emit_x64_vector: Provide AVX path for EmitVectorMaxS64()
2020-04-22 20:53:46 +01:00
Lioncash
2cac6ad129
emit_x64_vector: Simplify EmitVectorLogicalLeftShift8()
...
Similar to EmitVectorLogicalRightShift8(), we can determine a mask ahead
of time and just and the results of a halfword left shift.
2020-04-22 20:53:46 +01:00
Lioncash
135107279d
emit_x64_vector: Simplify EmitVectorLogicalShiftRight8()
...
We can generate the mask and AND it against the result of a halfword
shift instead of looping.
2020-04-22 20:53:46 +01:00
Lioncash
2952b46b16
emit_x64_vector: Amend value definition in SSE 4.1 path for EmitVectorSignExtend16()
...
We should be defining the value after the results have been calculated
to be consistent with the rest of the code.
2020-04-22 20:53:46 +01:00
Lioncash
fda19095ea
emit_x64_vector: Remove fallback in EmitVectorSignExtend64()
...
This is fairly trivial to do manually.
2020-04-22 20:53:46 +01:00
Lioncash
39593fcd26
emit_x64_vector: Remove fallback for EmitVectorSignExtend32()
...
We can just do the extension manually, which gets rid of the need to
fall back here.
2020-04-22 20:53:46 +01:00
Lioncash
053175f69b
ir_emitter: Rename fpscr_controlled parameters to fpcr_controlled
...
Part of addressing #333
2020-04-22 20:53:46 +01:00
MerryMage
f0184c4b8d
a32/exception_generating: BPKT: Define unpredictable behaviour
...
Define unpredictable behaviour to be BKPT executes conditionally
2020-04-22 20:53:46 +01:00
MerryMage
a12854857b
A32: Add define_unpredictable_behaviour option
2020-04-22 20:53:46 +01:00
MerryMage
b0abaa8312
A32/location_descriptor: Change formatting to use hex
2020-04-22 20:53:46 +01:00
MerryMage
ccbf6c7f63
microinstruction: A32ExceptionRaised causes CPU exception
2020-04-22 20:53:46 +01:00
MerryMage
6595e49a31
A32/types: CondToString: Add nv
2020-04-22 20:53:46 +01:00
MerryMage
d5b9c4a4bb
block_of_code: Hide NX support behind compiler flag
...
Systems that require W^X can use the DYNARMIC_ENABLE_NO_EXECUTE_SUPPORT cmake option.
2020-04-22 20:53:46 +01:00
MerryMage
de4494ffa5
Implement perfmap
2020-04-22 20:53:46 +01:00
MerryMage
f73104633b
a32_emit_x64: Fix incorrect BMI2 implementation for SetCpsr
...
* The MSB for each byte in cpsr_ge were not being appropriately set.
* We also expand test coverage to test this case.
* We fix the disassembly of the MSR (imm) and MSR (reg) instructions as well.
2020-04-22 20:53:46 +01:00
MerryMage
3432a08e0a
backend/x64: Support W^X systems
...
Closes #176 .
2020-04-22 20:53:46 +01:00
BreadFish64
2a65442933
Backend: Create "backend" folder
...
similar to the "frontend" folder
2020-04-22 20:53:46 +01:00
MerryMage
3b13f1eb12
A64/translate: Standardize arguments of helper functions
...
Don't pass in IREmitter when TranslatorVisitor is already available.
2020-04-22 20:53:45 +01:00
MerryMage
a4e556d59c
A64/translate: Standardize TranslatorVisitor abbreviation
...
Prefer v to tv.
2020-04-22 20:53:45 +01:00
MerryMage
9a0dc61efd
emit_x64_vector: Avoid recalculating addresses in EmitVectorTableLookup
2020-04-22 20:53:45 +01:00
Lioncash
3d465e2c36
A64: Implement SQXTN, SQXTUN, and UQXTN's scalar variants
...
We can implement these in terms of the vector variants
2020-04-22 20:53:45 +01:00
Lioncash
4ff39c6ea8
A64: Implement SDOT and UDOT's (by element) variants
...
Gets all of the dot product instructions out of the way.
2020-04-22 20:53:45 +01:00
MerryMage
21df1fb539
emit_x64_vector: Don't load zero constant from memory in EmitVectorTableLookup
2020-04-22 20:53:45 +01:00
MerryMage
3bbcca8757
emit_x64_vector: Special-case is_defaults_zero && table_size == 2 in EmitVectorTableLookup
2020-04-22 20:53:45 +01:00
MerryMage
9cc00f900c
emit_x64_vector: Release registers when possible in EmitVectorTableLookup
2020-04-22 20:53:45 +01:00
MerryMage
a12afd1065
reg_alloc: Add the ability to Release an allocation early
2020-04-22 20:53:45 +01:00
MerryMage
e68bd3c6c1
emit_x64_vector: Special-case table_size == 1 in EmitVectorTableLookup
2020-04-22 20:53:45 +01:00
MerryMage
a4e1f8a63a
emit_x64_vector: SSE4.1 implementation of EmitVectorTableLookup
2020-04-22 20:53:45 +01:00
MerryMage
0c18b85c27
A64: Implement TBL and TBX
2020-04-22 20:53:45 +01:00
MerryMage
89d08c7d61
IR: Add VectorTable and VectorTableLookup IR instructions
2020-04-22 20:53:45 +01:00
MerryMage
0288974512
opcodes: Cleanup opcodes table
...
* Remove T:: prefix from types.
* Add another column for a 4th argument.
2020-04-22 20:53:45 +01:00
Lioncash
d9fc6cf31f
A64: Implement SDOT and UDOT's vector variant
2020-04-22 20:53:45 +01:00
Lioncash
cb5e5c5d49
A64: Implement SADALP and UADALP
...
While we're at it we can join the code for SADDLP and UADDLP with these
instructions, since the only difference is we do an accumulate at the
end of the operation.
2020-04-22 20:53:45 +01:00
Lioncash
29f8b30634
A64: Implement SRSHL and URSHL
...
Implements both scalar and vector variants.
2020-04-22 20:53:45 +01:00
Lioncash
0efa2ce3b0
ir: Add opcodes for performing rounding left shifts
2020-04-22 20:53:45 +01:00
MerryMage
656ceff225
emit_x64_floating_point: Fix smallest normal check in EmitFPMulAdd
2020-04-22 20:53:45 +01:00
Lioncash
f3f60cd179
A64: Implement ISB
...
Given we want to ensure that all instructions are fetched again, we can
treat an ISB instruction as a code cache flush.
2020-04-22 20:53:45 +01:00
Lioncash
be53e356a2
A64: Implement FCVTN{2}
2020-04-22 20:53:45 +01:00
Lioncash
4c3d7c5a8d
A64: Implement FCVTL{2}
2020-04-22 20:53:45 +01:00
Lioncash
7eb6be7a6a
A64: Implement FMAXNM and FMINNM vector variants.
...
Currently we can implement these in terms of the scalar IR variants.
2020-04-22 20:53:45 +01:00
Lioncash
8b65ea68c0
A64: Implement FMAXP, FMAXNMP, FMINP, and FMINNMP's vector variants
...
We can just implement these in terms of scalars for the time being.
2020-04-22 20:53:45 +01:00
MerryMage
ec76f95f5a
emit_x64_vector_floating_point: Correct value of smallest_normal_number
2020-04-22 20:53:45 +01:00
MerryMage
e60d6c0d20
fp/info: Incorrect point_position in FPValue
2020-04-22 20:53:45 +01:00
MerryMage
8a3b6364c2
load_store_exclusive: Define s == t state to be Constraint_NONE
...
Downstream (yuzu) mentioned that the instruction:
STXR W9, W9, [X0]
was executed in the program "Crash N-Sane Trilogy".
2020-04-22 20:53:45 +01:00
MerryMage
cd40e4dae0
A64/translate: Allow for unpredictable behaviour to be defined
2020-04-22 20:53:45 +01:00
MerryMage
d1d6f4feb5
system: Implement MRS CNTFRQ_EL0
2020-04-22 20:53:45 +01:00
Lioncash
7ef7def661
A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants
...
Currently we implement these in terms of the scalar variants. Falling
back to the interpreter is slow enough to make it more effective than
doing that.
2020-04-22 20:46:23 +01:00
Lioncash
a4b0e2ace6
A64: Implement UQADD/UQSUB's scalar variants
2020-04-22 20:46:23 +01:00
Lioncash
acbaf04fef
ir: Add opcodes for unsigned saturating add and subtract
2020-04-22 20:46:23 +01:00
Lioncash
c41b5a3492
x64/reg_alloc: Use type alias for array returned by GetArgumentInfo()
...
This way if the number ever changes, we don't need to change the type in
other places.
2020-04-22 20:46:23 +01:00
Lioncash
2188765e28
ir/value: Use type alias CoprocessorInfo for std::array<u8, 8>
...
Provides a more descriptive label for the interface, and avoids the need
to hardcode the array size in multiple places.
2020-04-22 20:46:23 +01:00
MerryMage
71e137715d
status_register_access: Add support for bits 0 and 1 of mask to MSR
2020-04-22 20:46:23 +01:00
MerryMage
ac51c2547d
A32/translate/load_store: Correct detection of writeback
2020-04-22 20:46:23 +01:00
MerryMage
d345220251
A32/translate: Add TranslateSingleInstruction
2020-04-22 20:46:23 +01:00
MerryMage
5fc197c564
A32/ir_emitter: Bug fix: IREmitter::ExceptionRaised using incorrect opcode
2020-04-22 20:46:23 +01:00
MerryMage
ff3805e332
A32/decoders: Split instruction list into include file
2020-04-22 20:46:23 +01:00
MerryMage
3f4d118d73
microinstruction: Improve assert messages
2020-04-22 20:46:23 +01:00
MerryMage
a7e6f2a235
emit_x64_vector: EmitVectorNarrow16: AVX512 implementation
2020-04-22 20:46:23 +01:00
MerryMage
b6350e3947
emit_x64_vector: EmitVectorNarrow32: prefer pblendw to loading constant
2020-04-22 20:46:23 +01:00
MerryMage
8fdba189cb
emit_x64_vector: packusdw is SSE4.1
2020-04-22 20:46:23 +01:00
MerryMage
1ef388d1cd
emit_x64_vector_floating_point: Simplify FPVector{Min,Max}
2020-04-22 20:46:23 +01:00
MerryMage
4a1ce797cb
emit_x64_vector_floating_point: Simplify Get*Vector functions
2020-04-22 20:46:23 +01:00
MerryMage
bcaced297a
emit_x64_floating_point: Remove EmitProcessNaNs
2020-04-22 20:46:23 +01:00
MerryMage
2e0885388e
devirtualize: Replace DEVIRT macro with function template
2020-04-22 20:46:23 +01:00
Lioncash
54d8552177
a32_emit_x64: std::move A32::UserConfig in the constructor
...
This avoids a few redundant atomic increments and decrements,
considering the UserConfig instance contains a std::array of
std::shared_ptr<Coprocessor> instances.
2020-04-22 20:46:23 +01:00
MerryMage
b098c650df
emit_x64_floating_point: Use EmitPostProcessNaNs in EmitFPMulX
2020-04-22 20:46:23 +01:00
MerryMage
c1babf41b2
emit_x64_floating_point: Remove unnecessary DenormalsAreZero from EmitFPSingleToDouble and EmitFPDoubleToSingle
2020-04-22 20:46:23 +01:00
MerryMage
700088408d
emit_x64_floating_point: Simplify EmitFP{Min,Max}{,Numeric}{32,64}
2020-04-22 20:46:23 +01:00
MerryMage
07e0585994
emit_x64_floating_point: Reduce NaN processing overhead
2020-04-22 20:46:23 +01:00
MerryMage
f5e11d117a
A64: Implement FMULX, scalar single/double variant
2020-04-22 20:46:23 +01:00
MerryMage
17f73974f2
IR: Implement FPMulX IR instruction
2020-04-22 20:46:23 +01:00
Lioncash
391e16be64
emit_x64_vector: Vectorize 32-bit variants of paired min/max
...
Gets rid of the fallbacks for these cases.
2020-04-22 20:46:23 +01:00
MerryMage
5ae045d67e
emit_x64_vector: Improve code emission of VectorGetElement* for index == 0
2020-04-22 20:46:23 +01:00
MerryMage
e9ab7f7664
reg_alloc: Do a UseScratch if a Use destination is too small
2020-04-22 20:46:23 +01:00
MerryMage
90f8dda966
emit_x64_floating_point: AVX implementation of ForceToDefaultNaN
2020-04-22 20:46:23 +01:00
MerryMage
dfb660cd16
emit_x64_vector_floating_point: Prefer blendvp{s,d} to vblendvp{s,d} where possible
...
It's a cheaper instruction.
2020-04-22 20:46:23 +01:00
MerryMage
476c0f15da
backend_x64: Remove all use of xmm0
2020-04-22 20:46:23 +01:00
MerryMage
8252efd7b1
emit_x64_vector_floating_point: AVX implementation of ForceToDefaultNaN
2020-04-22 20:46:23 +01:00
MerryMage
746dc521b9
emit_x64_vector_floating_point: Reduce codesize of ForceToDefaultNaN
2020-04-22 20:46:23 +01:00
MerryMage
7731dcdca9
emit_x64_vector_floating_point: Reduce codesize of EmitTwoOpVectorOperation
2020-04-22 20:46:23 +01:00
MerryMage
bb93353f94
emit_x64_vector_floating_point: Correct FMA in FTZ mode
...
x64 rounds before flushing to zero
AArch64 rounds after flushing to zero
This difference of behaviour is noticable if something would round to a smallest normalized number
2020-04-22 20:46:23 +01:00
MerryMage
8ef195db3c
emit_x64_floating_point: DenormalsAreZero is redundant as hardware already does DAZ
...
Exceptions: F{MIN,MAX}{,NM}
2020-04-22 20:46:23 +01:00
MerryMage
de9d8c461c
emit_x64_floating_point: FlushToZero is redundant as hardware already does FTZ
2020-04-22 20:46:23 +01:00
MerryMage
822fd4a875
backend_x64: Fix FPVectorMulAdd and FPMulAdd NaN handling with denormals
...
Denormals should be treated as zero in NaN handler
2020-04-22 20:46:23 +01:00
MerryMage
b393e15ab6
backend_x64: Fix bugs when FPCR.FZ=1
...
Bugs:
* DenormalsAreZero flushed to positive zero instead of preserving sign.
* FMAXNM/FMINNM (scalar) should perform DAZ *before* special zero handling.
* FMAX/FMIN/FMAXNM/FMINNM (vector) did not DAZ.
2020-04-22 20:46:23 +01:00
MerryMage
5e88d66470
fp/info: Deduplicate functions
2020-04-22 20:46:23 +01:00
MerryMage
2019d32743
emit_x64_floating_point: Deduplicate EmitFPMulAdd implementation
2020-04-22 20:46:23 +01:00
MerryMage
e038fe72df
emit_x64_floating_point: Deduplicate code
2020-04-22 20:46:23 +01:00
MerryMage
ec82a845b7
emit_x64_vector_floating_point: Fix FPVector{Max,Min} when FPCR.DN = 1
2020-04-22 20:46:23 +01:00
MerryMage
7f27945411
emit_x64_floating_point: Fix FP{Max,Min} when FPCR.DN = 1
2020-04-22 20:46:23 +01:00
MerryMage
21a28c2545
IR: SSE4.1 implementation of FPVectorRoundInt
2020-04-22 20:46:23 +01:00
MerryMage
9669e49817
A64: Implement FRINT{N,M,P,Z,A,X,I} (vector), single/double variant
2020-04-22 20:46:23 +01:00
MerryMage
f976c47008
IR: Initial implementation of FPVectorRoundInt
2020-04-22 20:46:23 +01:00
MerryMage
f2393488fe
A64: Implement SQADD and SQSUB, scalar variant
2020-04-22 20:46:23 +01:00
MerryMage
10e196480f
IR: Generalise SignedSaturated{Add,Sub} to support more bitwidths
2020-04-22 20:46:23 +01:00
MerryMage
71db0e67ae
a64_emit_x64: Bugfix EmitA64OrQC - Incorrect argument
2020-04-22 20:46:23 +01:00
Lioncash
d0fdd3c6e6
simd_three_same: Extract non-paired SMAX, SMIN, UMAX, UMIN code to a common function
...
Deduplicates a bit of code and makes its layout consistent with the
paired variants
2020-04-22 20:46:23 +01:00
Lioncash
2bea2d0512
A64: Implement SMAXP, SMINP, UMAXP, UMINP
2020-04-22 20:46:23 +01:00
Lioncash
463b9a3d02
ir: Add opcodes for vector paired maximum and minimums
...
For the time being, we can just do a naive implementation which avoids
falling back to the interpreter a bit. Horizontal operations aren't
necessarily x86 SIMD's forte anyways.
2020-04-22 20:46:23 +01:00
Lioncash
43344c5400
A64: Implement SMAXV, SMINV, UMAXV, and UMINV
2020-04-22 20:46:23 +01:00
Lioncash
2501bfbfae
ir: Add opcodes for performing scalar integral min/max
2020-04-22 20:46:23 +01:00
Lioncash
7fdd8b0197
A64: Implement PMULL{2}
2020-04-22 20:46:23 +01:00
Lioncash
5ebf496d4e
translate: Deduplicate GetDataSize() functions
...
Avoids defining the same function multiple times in different files.
2020-04-22 20:46:22 +01:00
Lioncash
f83cd2da9a
floating_point_{conditional}_compare: Deduplicate code
...
Deduplicates the implementation code of instructions by extracting the
code to a common function.
2020-04-22 20:46:22 +01:00
MerryMage
f9c6d5e1a0
common: Move all cryptographic function to common/crypto
2020-04-22 20:46:22 +01:00
MerryMage
5dc23e49d7
a32_emit_x64: BMI2 implementation of A32SetCpsr
2020-04-22 20:46:22 +01:00
MerryMage
0f85305933
a32_emit_x64: Shorten EmitA32GetCpsr
2020-04-22 20:46:22 +01:00
MerryMage
9fe2bf8733
a32_emit_x64: Assert that memory layout assumption in EmitA32GetCpsr is valid
2020-04-22 20:46:22 +01:00
Lioncash
b48fb8ca6b
A64: Implement PMUL
2020-04-22 20:46:22 +01:00
Lioncash
affa312d1d
ir: Add opcode for performing polynomial multiplication
2020-04-22 20:46:22 +01:00
MerryMage
dd4ac86f8e
A64: Implement FCVT{N,M,A,P}{U,S} (vector), FCVTZU (vector, integer), single/double variant
2020-04-22 20:46:22 +01:00
MerryMage
28b38916a8
A64: Implement FCVTZS (vector, integer), single/double variant
2020-04-22 20:46:22 +01:00
MerryMage
507bcd8b8b
IR: Implement FPVectorTo{Signed,Unsigned}Fixed
2020-04-22 20:46:22 +01:00
MerryMage
8f75a1fe04
fp/info: Replace constant value generators with FPValue
...
Instead of having multiple different functions we can just have one.
2020-04-22 20:46:22 +01:00
MerryMage
da261772ea
emit_x64_vector_floating_point: AVX implementation of FPVector{Max,Min}
2020-04-22 20:46:22 +01:00
MerryMage
a0d6f0de57
emit_x64_vector_floating_point: Remove unnecessary double jump in HandleNaNs
2020-04-22 20:46:22 +01:00
Lioncash
c778c7b868
A64: Implement FMAX's vector single and double precision variants
2020-04-22 20:46:22 +01:00
Lioncash
009879d92b
A64: Implement FMIN's vector single and double precision variants
2020-04-22 20:46:22 +01:00
MerryMage
7b03da86c2
IR: Implement FPVector{Max,Min}
2020-04-22 20:46:22 +01:00
MerryMage
e76e1186bb
FPRecipEstimate: Move offset out of function
...
MSVC has weird lambda capturing rules.
2020-04-22 20:46:22 +01:00
MerryMage
ddcff86f9c
microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits
2020-04-22 20:46:22 +01:00
MerryMage
10de36394e
A64: Implement FRECPS, vector/scalar single/double variants
2020-04-22 20:46:22 +01:00
MerryMage
901bd9b4e2
IR: Implement FPRecipStepFused, FPVectorRecipStepFused
2020-04-22 20:46:22 +01:00
MerryMage
f66f61d8ab
A64: Implement FRECPE, vector single/double variant
2020-04-22 20:46:22 +01:00
MerryMage
939f5f5c7a
IR: Implement FPVectorRecipEstimate
2020-04-22 20:46:22 +01:00
MerryMage
27c73dd56a
A64: Implement FRECPE, scalar single/double variant
2020-04-22 20:46:22 +01:00
MerryMage
fc2d33ae7b
IR: Implement FPRecipEstimate
2020-04-22 20:46:22 +01:00
MerryMage
c1dcfe29f7
IR: Implement FPRecipEstimate
2020-04-22 20:46:22 +01:00
MerryMage
7a673a8a43
fp: Change FPUnpacked to a normalized representation
...
Having a known position for the highest set bit makes writing algorithms easier
2020-04-22 20:46:22 +01:00
MerryMage
3fe45c6d8e
block_of_code: Add ABI_PARAMS array
2020-04-22 20:46:22 +01:00
MerryMage
642b6c31d2
A64: Implement MLA, MLS (by element), vector single/double variant
2020-04-22 20:46:22 +01:00
MerryMage
0de37b11ad
A64: Implement FMLS (vector), single/double variant
2020-04-22 20:46:22 +01:00
MerryMage
64c2f698a2
emit_x64_vector_floating_point: Specify NanHandler::function_type explicitly
...
MSVC doesn't like dealing with auto return types
2020-04-22 20:46:22 +01:00
MerryMage
2ef59b4f03
emit_x64_vector_floating_point: ChooseOnFsize arguments maybe_unused
2020-04-22 20:46:22 +01:00
MerryMage
04f325a05e
IR: Implement FPVectorNeg
2020-04-22 20:46:22 +01:00
MerryMage
934132e0c5
A64: Implement FMLA (vector), single/double variant
2020-04-22 20:46:22 +01:00
MerryMage
771a4fc20b
IR: Implement FPVectorMulAdd
2020-04-22 20:46:22 +01:00
MerryMage
3218bb9890
emit_x64_vector_floating_point: Standardize naming scheme
2020-04-22 20:46:22 +01:00
MerryMage
8f72be0a02
emit_x64_floating_point: Simplify indexers
2020-04-22 20:46:22 +01:00
MerryMage
25b28bb234
emit_x64_vector_floating_point: Simplify EmitVectorOperation*
2020-04-22 20:46:22 +01:00
MerryMage
1edd0125b2
mp: rename mp.h to mp/function_info.h
2020-04-22 20:46:22 +01:00
MerryMage
0921678edb
emit_x64_vector: Slightly improve ArithmeticShiftRightByte
2020-04-22 20:46:22 +01:00
MerryMage
43407c4bb4
emit_x64_vector: Simplify VectorShuffleImpl
2020-04-22 20:46:22 +01:00
MerryMage
ecbf9dbae5
IR: Implement A64OrQC
2020-04-22 20:46:22 +01:00
MerryMage
f0fecf2615
A64: Implement UQSHRN, UQRSHRN (vector)
2020-04-22 20:46:22 +01:00
MerryMage
8f4c1a8558
emit_x64_vector: -0x80000000 isn't -0x80000000
2020-04-22 20:46:22 +01:00
MerryMage
b455b566e7
A64: Implement UQXTN (vector)
2020-04-22 20:46:22 +01:00
MerryMage
e686a81612
emit_x64_vector: Fix non-SSE4.1 saturated narrowing reconstruction comparison
...
Allows non-SSE4.1 to produce the correct FPSR.QC flag
2020-04-22 20:46:22 +01:00
MerryMage
3874cb37e3
A64: Implement SQXTN (vector)
2020-04-22 20:46:22 +01:00
MerryMage
8ef114d48f
emit_x64_vector: packusdw reqiures SSE4.1
...
In EmitVectorSignedSaturatedNarrowToUnsigned32.
2020-04-22 20:46:22 +01:00
MerryMage
712c6c1d7e
A64: Implement SQSHRUN, SQRSHRUN (vector)
2020-04-22 20:46:22 +01:00
MerryMage
c5722ec963
simd_shift_by_immediate: Simplify ShiftRight
2020-04-22 20:46:22 +01:00
MerryMage
f020dbe4ed
A64: Implement SQXTUN
2020-04-22 20:46:22 +01:00
MerryMage
6918ef7360
microinstruction: Reorganize FPSCR related instruction queries
2020-04-22 20:46:22 +01:00
Lioncash
a639fa5534
microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR()
...
These were forgotten when the opcodes were added.
2020-04-22 20:46:22 +01:00
Lioncash
3ca18d8a6d
u128: Make Bit() a const-qualified member function
...
This function doesn't modify the struct members, so it can be made
const.
2020-04-22 20:46:22 +01:00
MerryMage
b2e4c16ef8
A64: Implement FRSQRTS (vector), single/double variant
2020-04-22 20:46:22 +01:00
MerryMage
45dc5f74f3
A64: Implement FRSQRTE (vector), single/double variant
2020-04-22 20:46:22 +01:00
MerryMage
b74d5520f9
A64: Implement FRSQRTS (scalar), single/double variant
2020-04-22 20:46:22 +01:00
MerryMage
506e544bfe
IR: Implement FPRSqrtStepFused
2020-04-22 20:46:22 +01:00
MerryMage
6eb069e80d
fp: Implement FPRSqrtStepFused
2020-04-22 20:46:22 +01:00
MerryMage
b0ff35fcd1
fp: Implement FPNeg
2020-04-22 20:46:22 +01:00
MerryMage
ca6774ccce
process_nan: Add two operand variant
2020-04-22 20:46:22 +01:00
Lioncash
ace7d2ba50
A64: Implement FMAXP, FMINP, FMAXNMP and FMINNMP's scalar double/single-precision variant
2020-04-22 20:46:21 +01:00
MerryMage
66bb05fc0a
emit_x64_floating_point: Fixup special NaN case in FMA FPMulAdd implementation
2020-04-22 20:46:21 +01:00
Lioncash
070637e0f6
fp: Use a forward declaration in fused.h
...
It's permissible to forward declare here, so we can do so and eliminate
a direct header dependency
2020-04-22 20:46:21 +01:00
Lioncash
030820f649
u128: Implement comparison operators in terms of one another
...
We can just implement the comparisons in terms of operator< and
implement inequality with the negation of operator==.
2020-04-22 20:46:21 +01:00
MerryMage
76b07d6646
u128: StickyLogicalShiftRight requires special-casing for amount == 64
...
In this case (128 - amount) == 64, and this invokes undefined behaviour
2020-04-22 20:46:21 +01:00
Lioncash
49c7edf7c6
A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant
2020-04-22 20:46:21 +01:00
Lioncash
c704acafe4
A64: Implement FMUL (by element)'s scalar double/single-precision variant
2020-04-22 20:46:21 +01:00
MerryMage
0ce11b7b15
emit_x64_floating_point: Implement accurate fallback for FPMulAdd{32,64}
2020-04-22 20:46:21 +01:00
MerryMage
e199887fbc
fp: Implement FPMulAdd
2020-04-22 20:46:21 +01:00
MerryMage
53a8c15d12
process_nan: Add FPProcessNaNs3
2020-04-22 20:46:21 +01:00
MerryMage
1c8e93e74d
block_of_code: Add SysV ABI fifth and sixth parameters
2020-04-22 20:46:21 +01:00
MerryMage
1fe8f51c54
u128: Add StickyLogicalShiftRight
2020-04-22 20:46:21 +01:00
MerryMage
b0afd53ea7
u128: Add Multiply64To128
2020-04-22 20:46:21 +01:00
MerryMage
5566fab29a
u128: Add u128::Bit
2020-04-22 20:46:21 +01:00
MerryMage
3e62fea003
u128: Add comparison operators
2020-04-22 20:46:21 +01:00
MerryMage
f17cd6f2c5
unpacked: Use ResidualErrorOnRightShift in FPRoundBase
...
Fixes a bug relating to exponents that are severely out of range.
2020-04-22 20:46:21 +01:00
MerryMage
805428e35e
fp: Remove MantissaT
2020-04-22 20:46:21 +01:00
MerryMage
bda86fd167
FPRSqrtEstimate: Improve documentation of RecipSqrtEstimate
2020-04-22 20:46:21 +01:00
Lioncash
0a64a66b26
FPRSqrtEstimate: Deduplicate array bounds
...
Dehardcodes a few constants in the loops.
2020-04-22 20:46:21 +01:00
Lioncash
b7bd70fd19
A64: Implement FMAXV, FMINV, FMAXNMV, and FMINNMV
2020-04-22 20:46:21 +01:00
Lioncash
664fb12e21
FPRSqrtEstimate: Use forward declarations where applicable
2020-04-22 20:46:21 +01:00
Lioncash
3447c82656
translate: Return by bool in helpers where applicable
...
Gets rid of a bit of duplication regarding the early-out cases and makes
all helpers functions consistent (previously some had a return type of
bool, while others had a return type of void).
2020-04-22 20:46:21 +01:00
Lioncash
d65b056eba
Simplify fallback case for EmitVectorSetElement64()
2020-04-22 20:46:21 +01:00
MerryMage
6087c2af6f
emit_x64_floating_point: s/Esimate/Estimate/
2020-04-22 20:46:21 +01:00
MerryMage
f837ce8e78
simd_scalar_two_register_misc: Implement FRSQRTE, scalar variant
2020-04-22 20:46:21 +01:00
MerryMage
bde58b04d4
IR: Implement FPRSqrtEstimate
2020-04-22 20:46:21 +01:00
MerryMage
16061c28f3
simd_vector_x_indexed_element: Implement FMUL (by element), vector variant
2020-04-22 20:46:21 +01:00
MerryMage
55eaa16615
a64_emit_x64: Ensure host has updated ticks in EmitA64GetCNTPCT
...
Discovered by @Subv.
Fixes incomplete fix begun in 5a91c94dca47c9702dee20fbd5ae1f4c07eef9df.
That fix fails to take into account that LinkBlock doesn't update ticks until there
are no remaining ticks to be executed.
Test added to confirm fix.
2020-04-22 20:46:21 +01:00
MerryMage
edd795e991
a64_emit_x64: Fix stack misalignment on Windows for 128-bit exclusive writes
...
Discovered by @Subv.
Includes a test to ensure this codepath is exercised on Windows.
2020-04-22 20:46:21 +01:00
Lioncash
04b4c8b0cf
emit_x64_aes: Eliminate extraneous usage of a scratch register in EmitAESInverseMixColumns()
...
We can just use the same register the data is in as the result register,
eliminating the need to use a completely separate register to store the
result.
2020-04-22 20:46:21 +01:00
Lioncash
e5d80e998e
A64: Implement SADDLV
2020-04-22 20:46:21 +01:00
Lioncash
a1bc8ddb53
A64: Implement UADDLV
2020-04-22 20:46:21 +01:00
Lioncash
1dc1e3dcd8
fp: Use forward declarations where applicable
...
Minimizes the amount of files that need to be rebuilt if the headers
ever change.
2020-04-22 20:46:21 +01:00
Lioncash
46cb0d813b
emit_x64_vector: Append 'v' prefix onto movq in AVX path
...
This is something I missed when adding in the AVX broadcast code.
2020-04-22 20:46:21 +01:00
Subv
4606a081c9
A64: The A64SetTPIDR IR instruction writes to a system register and should not be eliminated by the dead code elimination pass.
...
Previously this instruction was alway eliminated, resulting in incorrect values for TPIDR_EL0.
2020-04-22 20:46:21 +01:00
MerryMage
b53127600b
fp: A64::FPCR -> FP::FPCR
2020-04-22 20:46:21 +01:00
MerryMage
084bf63a10
bit_util: Implement ClearBits and ModifyBits
2020-04-22 20:46:21 +01:00
MerryMage
699c5f36d5
system: Simplify static_cast
2020-04-22 20:46:21 +01:00
MerryMage
3f602129f4
system: Ensure value of CNTPCT_EL0 is accurate
...
Since we currently only update the host's tick count at the end of a
block, we force an end-of-block before executing a MRS %, CNTPCT_ELO
instruction.
2020-04-22 20:46:21 +01:00
Lioncash
84affdb260
safe_ops: Avoid cases where shift bases are invalid with signed values
...
For example, say the converted signed type is s64, shifting left by 63
bits would be undefined behavior.
However, given an ASL is essentially the same behavior as an LSL
we can just use an unsigned type instead of converting to a signed type.
2020-04-22 20:46:21 +01:00
Lioncash
d0274f412a
safe_ops: Avoid signed overflow in Negate()
...
Negation of values such as -9223372036854775808 can't be represented in
signed equivalents (such as long long), leading to signed overflow.
Therefore, we can just invert bits and add 1 to perform this behavior
with unsigned arithmetic.
2020-04-22 20:46:21 +01:00
Lioncash
af3e23b224
simd_scalar_shift_by_immediate: Implement FCVT{ZS, ZU} (vector, fixed-point)'s scalar double/single-precision variant
2020-04-22 20:46:21 +01:00
Lioncash
91abf87169
simd_scalar_two_register_misc: Implement FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU} (vector)'s scalar double/single-precision variants
...
We can simply implement this in terms of the fixed-point IR opcodes.
2020-04-22 20:46:21 +01:00
Lioncash
0ec8dac660
emit_x64: Remove FPSCR_RoundTowardsZero() virtual function from EmitContext struct
...
This code was bugged in that we were comparing if the rounding mode was
not equal to rounding towards zero. Fortunately, however, nothing uses
this function anymore, and there's already the more general
FPSCR_RMode() available, so this can be removed entirely.
2020-04-22 20:46:21 +01:00
Lioncash
fd92e2f186
emit_x64: Add missing <array> include
...
Commit 755adef62e504a8d616de9dda8937d2428a9471b introduced a helper
alias for std::array, eliminating the need to manually type out sizes
for them, however I forgot to add the include for <array>
2020-04-22 20:46:21 +01:00
Lioncash
f939bd0228
emit_x64_vector{_floating_point}: Add helper alias for sizing arrays relative to vector width
...
Avoids needing to remember to specify the proper size of the arrays, all
that's needed is to specify the type of the array and the size will
automatically be deduced from it. This helps prevent potential oversized
or undersized arrays from being specified.
2020-04-22 20:46:21 +01:00
MerryMage
58f3399032
A64/PopRSBHint: Prevent RETing to a guest PC of ~0ull from crashing the jit
2020-04-22 20:46:21 +01:00
MerryMage
e18fca17dc
A64: Implement FABD in terms of existing IR instructions
...
Fixes NaN issue. Closes #306 .
2020-04-22 20:46:21 +01:00
MerryMage
1dbe9d95e6
FPRoundInt: Final FPRound based on new sign
...
While this shouldn't change any of the results in theory, it's just logically more consistent
2020-04-22 20:46:21 +01:00
MerryMage
83be491875
emit_x64_floating_point: SSE4.1 implementation of EmitFPRound
2020-04-22 20:46:20 +01:00
MerryMage
a40127a054
A64: Implement FRINTX, FRINTI (scalar)
2020-04-22 20:46:20 +01:00
MerryMage
962fa3b65e
A64: Implement FRINTP, FRINTM, FRINTZ (scalar)
2020-04-22 20:46:20 +01:00
MerryMage
5200bf41cf
A64: Implement FRINTN (scalar)
2020-04-22 20:46:20 +01:00
MerryMage
8718dc1692
A64: Implement FRINTA (scalar)
2020-04-22 20:46:20 +01:00
MerryMage
b228694012
IR: Implement FPRoundInt
2020-04-22 20:46:20 +01:00
MerryMage
e24054f4d7
fp: Implement FPRoundInt
2020-04-22 20:46:20 +01:00
MerryMage
f876e4afa2
fp: Implement FPProcessNaN
2020-04-22 20:46:20 +01:00
MerryMage
591adee443
fp/info: Add DefaultNaN
2020-04-22 20:46:20 +01:00
MerryMage
797e18cd97
fp: Move FPToFixed to its own file
2020-04-22 20:46:20 +01:00
MerryMage
295deb4035
a64_jit_state: Add FPSR.QC flag
2020-04-22 20:46:20 +01:00
Lioncash
7797bc2fb2
emit_x64_vector: Use non-scratch Use* variants of registers within EmitVectorUnsignedAbsoluteDifference()
...
In some cases, a register isn't modified, depending on the branch taken,
so we can signify this by using the non-scratch variants in certain
cases.
2020-04-22 20:46:20 +01:00
Lioncash
f7f83b76b7
simd_scalar_two_register_misc: Implement scalar double/single-precision variants of FCM{EQ, GE, GT, LE, LT} (zero)
2020-04-22 20:46:20 +01:00
Lioncash
9db6d1e98b
translate_arm: Remove unnecessary rotr() function
...
We already have RotateRight() in our common code, so we can remove this
function and replace it with it. We can also implement ArmExpandImm_C()
in terms of ArmExpandImm().
2020-04-22 20:46:20 +01:00
Lioncash
9f8a44c982
cast_util: Remove unnecessary typename
...
Given we use std::aligned_storage_t, we don't need to specify
typename here. If we used std::aligned_storage, then we would need to.
2020-04-22 20:46:19 +01:00
MerryMage
89e43867c1
A64: Implement FADDP (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
33fa65de23
A64: Implement FADDP (vector)
2020-04-22 20:46:19 +01:00
MerryMage
9dba273a8c
A64: Implement SADDLP
2020-04-22 20:46:19 +01:00
MerryMage
70ff2d73b5
A64: Implement UADDLP
2020-04-22 20:46:19 +01:00
MerryMage
5563bbbd79
A64: Implement EXT
2020-04-22 20:46:19 +01:00
MerryMage
304cc7f61e
emit_x64_floating_point: SSE4.1 implementation for FP{Double,Single}ToFixed{S,U}{32,64}
2020-04-22 20:46:19 +01:00
MerryMage
3d9677d094
A64: Implement FCVTMU (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
79c9018d60
A64: Implement FCVTMS (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
49c4499a87
A64: Implement FCVTPU (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
af661ef5a6
A64: Implement FCVTPS (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
27319822bb
A64: Implement FCVTAU (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
c0c7a26314
A64: Implement FCVTAS (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
a1965a74a0
A64: Implement FCVTNU (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
7d36dbcdfd
A64: Implement FCVTNS (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
617ca0adf0
floating_point_conversion_integer: Refactor implementation of FCVTZS_float_int and FCVTZU_float_int
2020-04-22 20:46:19 +01:00
MerryMage
caaf36dfd6
IR: Initial implementation of FP{Double,Single}ToFixed{S,U}{32,64}
...
This implementation just falls-back to the software floating point implementation.
2020-04-22 20:46:19 +01:00
MerryMage
760cc3ca89
EmitContext: Expose FPCR
2020-04-22 20:46:19 +01:00
MerryMage
9571269552
fp/op: Implement FPToFixed
2020-04-22 20:46:19 +01:00
MerryMage
8087e8df05
mantissa_util: Implement ResidualErrorOnRightShift
...
Accurately calculate residual error that is shifted out
2020-04-22 20:46:19 +01:00
MerryMage
8668d61881
fp/unpacked: Implement FPRound
2020-04-22 20:46:19 +01:00
MerryMage
55d590c01f
FPCR: Add AHP setter and FZ16 getter
2020-04-22 20:46:19 +01:00
MerryMage
7360a2579b
mp: Implement metaprogramming library
2020-04-22 20:46:19 +01:00
MerryMage
4ab029c114
fp: Implement FPUnpack
2020-04-22 20:46:19 +01:00
MerryMage
4875658917
fp: Implement FPProcessException
2020-04-22 20:46:19 +01:00
MerryMage
3cb98e1560
fp: Move fp_util to fp/util
2020-04-22 20:46:19 +01:00
MerryMage
c41a38b13e
fp: Add FPSR
2020-04-22 20:46:19 +01:00
MerryMage
66381352f3
fp: Add FPInfo
...
Provides information about floating-point format for various bit sizes
2020-04-22 20:46:19 +01:00
MerryMage
d21659152c
safe_ops: Implement safe shifting operations
...
Implement shifiting operations that perform consistently across architectures
without running into undefined or implemented-defined behaviour.
2020-04-22 20:46:19 +01:00
MerryMage
b00fe23b91
bit_util: Implement MostSignificantBit
2020-04-22 20:46:19 +01:00
MerryMage
95ad0d0a66
bit_util: Use Ones to implement Bits
2020-04-22 20:46:19 +01:00
MerryMage
62b640b2fa
bit_util: Add ClearBit and ModifyBit
2020-04-22 20:46:19 +01:00
MerryMage
8651c2d10e
u128: Implement u128
...
For when we need a 128-bit integer
2020-04-22 20:46:19 +01:00
Lioncash
e7409fdfe4
A64: Implement UCVTF (vector, integer)'s double/single-precision variant
2020-04-22 20:46:19 +01:00
Lioncash
4aa4885ba7
ir: Add opcodes for vector conversion of u32/u64 to floating-point
2020-04-22 20:46:19 +01:00
Lioncash
fcae4e2418
simd_three_different: Deduplicate common implementations
...
Generally, the only difference between the signed variants and the
unsigned variants is whether or not we use a sign-extension or
zero-extension, so we can simply use common functions to implement both
cases without totally duplicating code twice here.
2020-04-22 20:46:19 +01:00
Lioncash
9c0d5cf15c
floating_point_conversion_integer: Handle S64/U64 -> F32 conversions in SCVTF_float_int and UCVTF_float_int
2020-04-22 20:46:19 +01:00
Lioncash
7a84b6e8d8
ir: Add opcodes for converting S64 and U64 to single-precision floating-point values
2020-04-22 20:46:19 +01:00
Lioncash
066061fa50
constant_pool: Remove unnecessary std::memset from constructor
...
AllocateFromCodeSpace() already zeroes out the allocated memory.
2020-04-22 20:46:19 +01:00
Lioncash
a1d6a86e8c
A64: Implement ADDV
2020-04-22 20:46:19 +01:00
Lioncash
35026a6ce3
emit_x64_vector: Vectorize fallback path for EmitVectorMaxU32()
2020-04-22 20:46:19 +01:00
Lioncash
245c903129
simd_three_same: Join FPAbsoluteComparison() into FPCompareRegister()
...
These are part of the same comparison family, so there's no real point
in keeping them separate.
2020-04-22 20:46:19 +01:00
Lioncash
9912836b59
A64: Implement scalar double/single-precision variants of FACGE, FACGT, FCMEQ, FCMGE, FCMGT
2020-04-22 20:46:18 +01:00
MerryMage
0b97e9bd8d
emit_x64_floating_point: Fix EmitFPU64ToDouble for TowardsMinusInfinity rounding mode
2020-04-22 20:46:18 +01:00
MerryMage
a2eb9a02e0
backend_x86: Add FPSCR_RMode to EmitContext
2020-04-22 20:46:18 +01:00
MerryMage
d875c08ebf
fp: Extract common RoundingMode enum
2020-04-22 20:46:18 +01:00
Lioncash
3714bc0ed4
floating_point_conversion_integer: Use FPS64ToDouble and FPU64ToDouble in SCVTF_float_int and UCVTF_float_int
...
The opcodes introduced in 979b6f39f1621b80bd463645ec5b08661cb6b1bf can
also be used here, avoiding more falling back to the interpreter.
2020-04-22 20:46:18 +01:00
Lioncash
b97358075e
simd_scalar_two_register_misc: Handle 64-bit case in SCVTF and UCVTF's scalar double/single-precision variant
...
Avoids falling back to the interpreter in the 64-bit case.
2020-04-22 20:46:18 +01:00
Lioncash
7252293184
emit_x64_floating_point: Correct use of UseGpr() in EmitFPU32ToDouble() and EmitFPU32ToSingle()
...
In the non-AVX512 path, the following code is present:
code.mov(from.cvt32(), from.cvt32());
since this potentially modifies 'from', we should be using
UseScratchGpr() instead.
2020-04-22 20:46:18 +01:00
Lioncash
fbd7623fe5
emit_x64_floating_point: Add AVX512F conversion operations to EmitFPU32ToSingle() and EmitFPU32ToDouble()
...
AVX-512F provides convenient instructions for these kinds of conversions
directly
2020-04-22 20:46:18 +01:00
Lioncash
3a41465eaf
ir: Add opcodes for converting S64 and U64 to double-precision values
2020-04-22 20:46:18 +01:00
MerryMage
436ca80bcd
Merge branch 'global_monitor'
2020-04-22 20:46:18 +01:00
Lioncash
0f4bf26e05
simd_two_register_misc: Utilize FPVectorAbs in FABS implementations
...
Since we already have opcodes introduced to implement FACGE and FACGT,
we can reutilize it for the FABS implementations.
2020-04-22 20:46:18 +01:00
MerryMage
821cff1227
A64: Add ClearExclusiveState method
2020-04-22 20:46:18 +01:00
Lioncash
81e572c78c
ir: Extend FPVectorAbs opcode to also handle 16-bit elements for FP16
2020-04-22 20:46:18 +01:00
MerryMage
2a8de5f733
a64_emit_x64: Clear exclusive state in EmitA64CallSupervisor
...
The kernel would have to execute an ERET instruction to return to
userland; this clears exclusive state.
2020-04-22 20:46:18 +01:00
Lioncash
53dbb6a92a
A64: Implement FACGE's vector single/double precision variants
2020-04-22 20:46:18 +01:00
MerryMage
57f7c7e1b0
Implement global exclusive monitor
2020-04-22 20:46:18 +01:00
Lioncash
6912a02d9b
A64: Implement FACGT's vector single/double precision variants
2020-04-22 20:46:18 +01:00
MerryMage
85234338d3
a64_emit_x64: Simplify EmitExclusiveWrite
2020-04-22 20:46:18 +01:00
Lioncash
fc731dddae
ir: Add opcodes for performing vector absolute floating-point values
...
This will be usable for implementing FACGE and FACGT
2020-04-22 20:46:18 +01:00
MerryMage
2fc6b33829
CMakeLists: Add missing files
2020-04-22 20:46:18 +01:00
Lioncash
0bee648b4f
emit_x64_vector: Deduplicate a bit of code in EmitVectorSetElement{8, 32, 64} functions
...
Given both branches are the same, we can hoist out the common code.
2020-04-22 20:46:18 +01:00
Lioncash
d86fea0d28
A64: Implement FCMEQ (zero)'s vector single and double precision variant
2020-04-22 20:46:18 +01:00
Lioncash
593eca7fb1
A64: Implement load/store single structure instructions
...
Implements LD{1, 2, 3, 4}, LD{1, 2, 3, 4}R, and ST{1, 2, 3, 4} single
structure variants.
2020-04-22 20:46:18 +01:00
Lioncash
9bec354791
A64: Implement FCMEQ (register)'s vector single and double precision variant
2020-04-22 20:46:18 +01:00
Lioncash
b6e223fc58
emit_x64_vector: Deduplicate a bit of code within EmitVectorGetElement8()
...
Given both branches use the same destination register size, we can hoist
the common code out.
2020-04-22 20:46:18 +01:00
Lioncash
5ce187a54e
ir: Add opcodes for floating-point vector equalities
2020-04-22 20:46:18 +01:00
MerryMage
be354dbfd0
ir/basic_block: Add missing U16 immediate type to DumpBlock
2020-04-22 20:46:18 +01:00
Lioncash
cf188448d4
emit_x64_vector: Vectorize fallback case in EmitVectorMultiply64()
...
Gets rid of the need to perform a fallback.
2020-04-22 20:46:18 +01:00
MerryMage
5503ff28c3
llvm_disassemble: Allow disassembly of invalid AArch64 instructions
2020-04-22 20:46:18 +01:00
Lioncash
954deff2d4
emit_x64_vector: Add break to final case in EmitVectorRoundingHalvingAddUnsigned()
...
This doesn't alter behavior but does make the code better if anything
else is ever added to this function in the future.
2020-04-22 20:46:18 +01:00
Lioncash
11a92eaaef
A64: Implement SRHADD and URHADD
2020-04-22 20:46:18 +01:00
Lioncash
9e75d08860
A64: Implement FABD's scalar single/double precision variant
2020-04-22 20:46:18 +01:00
Lioncash
bc718c5b28
ir: Add opcodes for performing rounding halving adds
2020-04-22 20:46:18 +01:00
Lioncash
d898d1779d
A64: Implement FABD's vector single/double precision variant
2020-04-22 20:46:18 +01:00
Lioncash
054549da35
emit_x64_vector: Simplify AVX-512 codepath in EmitVectorMultiply64
...
I realized I introduced a helper for simple AVX operation emitting, so
use that instead of writing it all out long-form.
2020-04-22 20:46:18 +01:00
Lioncash
8a4f8aed06
ir: Add opcode for performing FP vector absolute differences
2020-04-22 20:46:18 +01:00
Lioncash
cb456f914b
A64: Implement UMLAL{2}, UMLSL{2}, and UMULL{2}
...
Now that we have the helper function set up for the signed variants, we
can also modify it to be used with the unigned ones by performing a zero
extension instead of a sign extension.
2020-04-22 20:46:18 +01:00
MerryMage
ba84e7a8de
A64: Implement FNMSUB
2020-04-22 20:46:18 +01:00
Lioncash
3576c02d91
A64: Implement SMLSL{2}
2020-04-22 20:46:18 +01:00
MerryMage
a1042cfcd8
A64: Implement FNMADD
2020-04-22 20:46:18 +01:00
Lioncash
ada5c0b2fa
A64: Implement SMLAL{2}
2020-04-22 20:46:18 +01:00
MerryMage
0d83032a6f
A64: Implement FMSUB
2020-04-22 20:46:18 +01:00
Lioncash
2d1aca25e6
A64: Implement SMULL{2}
2020-04-22 20:46:18 +01:00
MerryMage
69e00d225c
A64: Implement FMADD
2020-04-22 20:46:18 +01:00
MerryMage
8c90fcf58e
IR: Implement FPMulAdd
2020-04-22 20:46:18 +01:00
Lioncash
c5ae9107a9
A64: Implement SABAL/SABAL2 and SABDL/SABDL2
...
Now that we have a helper function for the unsigned variants, we can
modify it to also be usable with the signed variants.
2020-04-22 20:46:18 +01:00
Lioncash
24e3299276
A64: Implement FCMGT, FCMGE (register) vector double and single precision variants
2020-04-22 20:46:18 +01:00
Lioncash
26d4473851
A64: Implement UABAL/UABAL2
2020-04-22 20:46:18 +01:00
Lioncash
350bc70be8
A64: Implement FCMGT, FCMGE, FCMLE, FCMLT (zero) vector double and single precision variants.
2020-04-22 20:46:18 +01:00
Lioncash
3397742c74
A64: Implement UABDL/UABDL2
2020-04-22 20:46:18 +01:00
Lioncash
c695da1cf3
ir: Add opcode for floating-point GE and GT comparisons
...
The rest of the comparisons can be implemented in terms of these two
2020-04-22 20:46:18 +01:00
Lioncash
6de5ed96e5
emit_x64_vector: Emit VPMULLQ in EmitVectorMultiply64 on AVX-512{DQ, VL} capable CPUs
...
Shortens code-gen down to a single instruction in the 64-bit path.
2020-04-22 20:46:18 +01:00
Lioncash
9054d1c20b
A64: Implement LDR (literal, SIMD&FP)
2020-04-22 20:46:18 +01:00
Lioncash
0da5e949a8
Correct typo in DataCacheOperation enum
...
Fixes a typo for the InvalidateByVAToPoC enum entry. Given yuzu is the
only known user of 64-bit mode and it doesn't use this value, we can get
away with changing this.
2020-04-22 20:46:18 +01:00
Lioncash
9736e2cce2
A64: Implement FABS' half-precision variant
2020-04-22 20:46:18 +01:00
Lioncash
6e5750e4ec
A64: Implement FABS' single and double precision variant
2020-04-22 20:46:18 +01:00
Lioncash
7bce8d8757
A64: Implement URSHR (scalar) and URSRA (scalar)
...
Now that the utility function is all set up from implementing SRSRA, the
unsigned variants can now be trivially implemented by modifying the
utility function to perform a logical shift right instead of an
arithmetical shift right for the unsigned case.
2020-04-22 20:46:18 +01:00
Lioncash
1e70a589b0
A64: Implement SRSRA (scalar)
2020-04-22 20:46:18 +01:00
Lioncash
998aef07f6
A64: Implement SRSHR (scalar)
2020-04-22 20:46:17 +01:00
Lioncash
7c0250e9f8
A64: Implement SABA
2020-04-22 20:46:17 +01:00
Lioncash
f00789e6f7
A64: Implement SABD
2020-04-22 20:46:17 +01:00
Lioncash
1e10017f4b
ir: Add opcodes for signed absolute differences
2020-04-22 20:46:17 +01:00
Tillmann Karras
d3b44c1b5a
decoder_detail: use structured bindings
2020-04-22 20:46:17 +01:00
Lioncash
f745eb28bf
simd_two_register_misc: Handle 64-bit case for SCVTF_int_4
2020-04-22 20:46:17 +01:00
Lioncash
3f6c529da2
ir: Add opcode to perform the vector conversion S64->F64
...
Unfortunately x86 prior to AVX-512 doesn't really give us any convenient instruction to do the work for us
2020-04-22 20:46:17 +01:00
Lioncash
0e61ee6bf6
A64: Implement SHLL/SHLL2
2020-04-22 20:46:17 +01:00
Lioncash
43e6e98c3b
A64: Add missing decoding for PRFM (unscaled offset)
2020-04-22 20:46:17 +01:00
Lioncash
f2a85d5601
A64: Implement UHSUB
2020-04-22 20:46:17 +01:00
Lioncash
b33360a324
A64: Implement SHSUB
2020-04-22 20:46:17 +01:00
Lioncash
44a5f8095a
ir: Add opcodes for performing vector halving subtracts
2020-04-22 20:46:17 +01:00
Lioncash
4f37c0ec5a
A64: Implement SM4EKEY
2020-04-22 20:46:17 +01:00
Lioncash
3bde3347a5
A64: Implement SM4E
2020-04-22 20:46:17 +01:00
Lioncash
b312d28295
ir: Add an opcode for doing an SM4 lookup table query
2020-04-22 20:46:17 +01:00
Lioncash
27a6d5f6ce
emit_x64_vector: Use VPOPCNTB in EmitVectorPopulationCount() if AVX-512 BITALG is available
2020-04-22 20:46:17 +01:00
Lioncash
4dcc7724e0
A64: Implement UHADD
2020-04-22 20:46:17 +01:00
Lioncash
f8714f7250
A64: Implement SHADD
2020-04-22 20:46:17 +01:00
Lioncash
089096948a
ir: Add opcodes for performing halving adds
2020-04-22 20:46:17 +01:00
Lioncash
3d00dd63b4
emit_x64_vector: Emit VPMINSQ and VPMINUQ for 64-bit vector min operations if AVX-512VL is available
2020-04-22 20:46:17 +01:00
Lioncash
b97b71b8aa
emit_x64_vector: Emit VPMAXSQ and VPMAXUQ for 64-bit vector max operations if AVX-512VL is available
2020-04-22 20:46:17 +01:00
Lioncash
033e400df0
emit_x64_vector_floating_point: Deduplicate accurate NaN handling code
...
Allows the code to both be used from the 32 bit and 64 bit operations without duplicating code.
2020-04-22 20:46:17 +01:00
Lioncash
0f067b7330
emit_x64_vector: Emit VPABSQ in EmitVectorAbs() for the 64-bit case if AVX-512VL is available
2020-04-22 20:46:17 +01:00
Lioncash
d4ee878cbd
emit_x64_vector: Use VPSRAQ in EmitVectorArithmeticShiftRight64() if AVX-512VL is available
2020-04-22 20:46:17 +01:00
Lioncash
b38dd191bd
disassembler_arm: Remove rotation helper function in favor of Common::RotateRight
...
Mildly reduces the amount of duplicated behavior
2020-04-22 20:46:17 +01:00
Lioncash
51e4f1d9db
emit_x64_vector: Vectorize fallback path of EmitVectorMaxS32()
2020-04-22 20:46:17 +01:00
Lioncash
c692ccdd6d
emit_x64_vector: Vectorize fallback path of EmitVectorMaxS8()
2020-04-22 20:46:17 +01:00
Lioncash
b194313d8c
emit_x64_vector: Vectorize fallback path in EmitVectorMinU32()
2020-04-22 20:46:17 +01:00
Lioncash
7ceda6d919
emit_x64_vector: Vectorize fallback path in EmitVectorMinU16()
2020-04-22 20:46:17 +01:00
Lioncash
cda85a1da0
emit_x64_vector: Vectorize fallback path in EmitVectorMinS32()
2020-04-22 20:46:17 +01:00
Lioncash
6e08eed210
emit_x64_vector: Vectorize fallback path in EmitVectorMinS8()
2020-04-22 20:46:17 +01:00
Lioncash
0fb6dce689
emit_x64_vector: Remove unnecessary if constexpr expression in LogicalVShift
...
This can simply be merged with the previous one.
2020-04-22 20:46:17 +01:00
Lioncash
5b71b1337b
emit_x64_vector: Avoid left shift of negative value in LogicalVShift
...
Now that we handle the signed variants, we also have to be careful about left shifts with negative values,
as this is considered undefined behavior.
2020-04-22 20:46:17 +01:00
Lioncash
9954d28868
a64_jitstate: Zero SP and PC on construction of A64JitState
...
Given we zero out/reset everything else in the struct, do the same for these members to keep initialization consistent
2020-04-22 20:46:17 +01:00
Lioncash
4efbd40ea4
backend_x64/callback: Default virtual destructor in the cpp file
...
Prevents the vtable being generated in each translation unit that includes the header (and silences -Wweak-vtables warnings)
2020-04-22 20:46:17 +01:00
Lioncash
edd0b5c8c7
a32_interface/a64_interface: Change reinterpret_casts to static_casts in GetCurrentBlock thunks
...
It's well-defined to static_cast a void* to its proper type.
2020-04-22 20:46:17 +01:00
Lioncash
e71612d394
A64: Implement SSHL (scalar)
2020-04-22 20:46:17 +01:00
Lioncash
ef1e69a1e3
A64: Implement SSHL (vector)
2020-04-22 20:46:17 +01:00
Lioncash
21974ee57e
backend_x64/ir: Amend generic LogicalVShift() template to also handle signed variants
...
Also adds IR opcodes to dispatch said variants
2020-04-22 20:46:17 +01:00
Lioncash
9fc89f0a0e
emit_x64_vector_floating_point: Use arrays for retrieving size instead of hardcoding the size
...
Similar changes were done in emit_x64_vector, but these were missed.
2020-04-22 20:46:17 +01:00
Lioncash
af28e89a13
emit_x64_vector: Vectorize fallback path in EmitVectorMaxU16()
2020-04-22 20:46:17 +01:00
Lioncash
cda75e2079
A64: Implement CMTST's scalar variant
2020-04-22 20:46:17 +01:00
Lioncash
0d20423ad5
emit_x64_vector: Vectorize non-SSE4.1 fallback path for VectorMultiply32()
2020-04-22 20:46:17 +01:00
Lioncash
d70ee7c0d1
emit_x64_vector: Use VBPROADCAST where applicable and available
...
Uses the instruction that does what it says in its name if available. Allows avoiding the use
of a scratch register in EmitVectorBroadcast8() and EmitVectorBroadcastLower8()'s SSSE3 path.
2020-04-22 20:46:17 +01:00
Lioncash
bebe7235ae
A64: Implement UZP1 and UZP2
2020-04-22 20:46:17 +01:00
Lioncash
26d77c6f09
ir: Add opcodes for performing vector deinterleaving
2020-04-22 20:46:17 +01:00
Lioncash
d6f9ed47d9
A64: Implement FNEG (half-precision)
2020-04-22 20:46:17 +01:00
Lioncash
7efbd73bac
A64: Implement USHL (scalar)
2020-04-22 20:46:17 +01:00
Lioncash
41f4717f2b
A64: Implement FNEG (vector)
2020-04-22 20:46:17 +01:00
Lioncash
ba1cc6366d
A64: Implement RSUBHN/RSUBHN2
2020-04-22 20:46:17 +01:00
Lioncash
e41640fe33
A64: Implement RADDHN/RADDHN2
2020-04-22 20:46:17 +01:00
Lioncash
b719a6b3f7
A64: Implement XAR
2020-04-22 20:46:17 +01:00
Lioncash
0b1b131ec2
simd_two_register_misc: Factor out common comparison code
...
Gets rid of a tiny bit of duplicated code.
2020-04-22 20:46:17 +01:00
Lioncash
ed0b84da70
A64: Implement CMLE (zero)'s vector variant
2020-04-22 20:46:17 +01:00
Lioncash
b595a68ffa
A64: Implement CMTST (vector)
2020-04-22 20:46:17 +01:00
Lioncash
48c7f8630c
A64: Implement ADDHN{2} and SUBHN{2}
2020-04-22 20:46:17 +01:00
Lioncash
3acd9c9200
translate: zero extend result in Vpart when storing to lower part of vector
2020-04-22 20:46:17 +01:00
Lioncash
87ca63699f
emit_x64_vector: Emit PMAXUD in EmitVectorMaxU32 on SSE4.1-capable CPUs
2020-04-22 20:46:17 +01:00
Lioncash
f17702f608
emit_x64_vector: Emit PMINUD in EmitVectorMinU32 on SSE4.1-capable CPUs
2020-04-22 20:46:17 +01:00
Lioncash
596a8dd1dd
emit_x64_vector: Emit PMINSD in EmitVectorMinS32 on SSE4.1-capable CPUs
...
Provides a better alternative to a fallback operation.
2020-04-22 20:46:17 +01:00
Lioncash
75fd4eaaaa
emit_x64_vector: Get rid of some magic numbers in loop bounds
2020-04-22 20:46:17 +01:00
Lioncash
7b80ac25eb
emit_x64_vector: Generify variable shift functions
2020-04-22 20:46:17 +01:00
Lioncash
4ec735f707
A64: Implement CMLE (zero)'s scalar variant
2020-04-22 20:46:17 +01:00
Lioncash
6534184df2
A64: Implement CMLT (zero)'s scalar single/double-precision variant
2020-04-22 20:46:17 +01:00
Lioncash
8863c9bb4b
A64: Implement SHA512H2
2020-04-22 20:46:17 +01:00
Lioncash
033b890e25
A64: Implement SHA512H
2020-04-22 20:46:17 +01:00
Lioncash
d1f5b084b4
A64: Handle S32->F32 case for SCVTF (vector)
2020-04-22 20:46:17 +01:00
Lioncash
38fa984b53
IR: Add opcode for packed word->f32 conversions
2020-04-22 20:46:16 +01:00
Lioncash
b8587d8e34
A64: Implement SHA512SU1
2020-04-22 20:46:16 +01:00
Lioncash
44d846045a
A64: Implement SHA512SU0
2020-04-22 20:46:16 +01:00
Lioncash
ca903c1585
A64: Implement SHA256H and SHA256H2
2020-04-22 20:46:16 +01:00
MerryMage
e4237c44eb
A64: Implement SCVTF (vector, integer), scalar varaint
2020-04-22 20:46:16 +01:00
MerryMage
bfba38d0b6
impl: Reorganize scalar two-register misc instructions
2020-04-22 20:46:16 +01:00
Lioncash
ea582b17cc
A64: Implement SHA256SU1
2020-04-22 20:46:16 +01:00
Lioncash
06c5dcaf5e
simd_two_register_misc: Add missing zeroing of the vector for CMGT and CMLT
2020-04-22 20:46:16 +01:00
Lioncash
0d50d7314b
A64: Implement CMGE (zero)'s vector variant
2020-04-22 20:46:16 +01:00
Lioncash
ab35dc0e78
A64: Implement MLS (by element)
2020-04-22 20:46:16 +01:00
Lioncash
1651e60462
A64: Implement MUL (by element)
2020-04-22 20:46:16 +01:00
MerryMage
a86d4093cd
A64: Implement MLA (by element)
2020-04-22 20:46:16 +01:00
Lioncash
7f47402609
A64: Implement ABS (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
c8eb4528be
A64: Implement SHA256SU0
2020-04-22 20:46:16 +01:00
Lioncash
181c3b0790
A64: Implement SHA1M
2020-04-22 20:46:16 +01:00
Lioncash
47bc97a71b
A64: Implement SHA1P
2020-04-22 20:46:16 +01:00
Lioncash
718f3e9bb4
A64: Implement scalar variants of CMEQ, CMGT, and CMGE zero comparison instructions
...
These can trivially use the ScalarCompare helper function.
2020-04-22 20:46:16 +01:00
Lioncash
3ad4e547e4
A64: Implement scalar variant of NEG
2020-04-22 20:46:16 +01:00
Lioncash
b4f3051e4b
simd: Relocate REV16, REV32 and REV64 vector variants to the proper file
...
These aren't scalar instruction variants.
2020-04-22 20:46:16 +01:00
Lioncash
19e276d10f
A64: Implement CMEQ (register, scalar)
2020-04-22 20:46:16 +01:00
Lioncash
5b8c9e5146
A64: Implement CMHS (register, scalar)
2020-04-22 20:46:16 +01:00
Lioncash
78bb12276a
A64: Implement CMHI (register, scalar)
2020-04-22 20:46:16 +01:00
Lioncash
c18b20b8d1
A64: Implement CMGE (register, scalar)
2020-04-22 20:46:16 +01:00
Lioncash
755981d0da
A64: Implement CMGT (register, scalar)
2020-04-22 20:46:16 +01:00
Lioncash
da6627124b
A64: Implement SHA1C
2020-04-22 20:46:16 +01:00
Lioncash
3c013bd9f8
A64: Implement SLI (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
154cac594a
A64: Implement SRI (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
6bcfdba1ad
general: Remove unused lambda captures
...
Resolves warnings that occur in Xcode 9.3
2020-04-22 20:46:16 +01:00
Lioncash
205ca6b4cb
A64: Implement SHA1SU1
2020-04-22 20:46:16 +01:00
Lioncash
16a001b9ff
A64: Implement SHA1SU0
2020-04-22 20:46:16 +01:00
Lioncash
3b6db59850
A64: Implement TRN2
2020-04-22 20:46:16 +01:00
Lioncash
30e158f8d0
A64: Implement TRN1
2020-04-22 20:46:16 +01:00
Lioncash
52cad2d9d0
A64: Implement SSRA (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
255a33936d
A64: Implement SSHR (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
6723b00497
A64: Implement USRA (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
d56fa8f735
A64: Implement USHR (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
870e418b0b
A64: Implement SHL (scalar)
2020-04-22 20:46:16 +01:00
Lioncash
97f2bea4f2
A64: Implement SM3PARTW1
2020-04-22 20:46:16 +01:00
Lioncash
e268b110f0
simd_sha512: Simplify RAX1
...
Now that the vector rotation helpers are in, replace the explicit
shifting with the relevant helper function that does the same thing.
Simply tidies up code; no behavioral changes are made.
2020-04-22 20:46:16 +01:00
Lioncash
20d2491267
A64: Implement SM3PARTW2
2020-04-22 20:46:16 +01:00
Lioncash
e1b662e90c
ir: Add helper functions for vector rotation
2020-04-22 20:46:16 +01:00
Lioncash
8a60a63a8b
A64: Implement SM3TT2B
2020-04-22 20:46:16 +01:00
Lioncash
b3d4c02098
A64: Implement SM3TT2A
2020-04-22 20:46:16 +01:00
Lioncash
7fbccabd81
A64: Implement SM3TT1B
2020-04-22 20:46:16 +01:00
Lioncash
769373b3ed
A64: Implement SM3TT1A
2020-04-22 20:46:16 +01:00
Lioncash
2d269fdcc7
simd_shift_by_immediate: Merge signed/unsigned helper functions
...
Gets rid of a little more code duplication.
2020-04-22 20:46:16 +01:00
Lioncash
d5461be6b4
A64: Implement SM3SS1
2020-04-22 20:46:16 +01:00
Lioncash
2db032ac83
A64: Implement SRI (vector)
2020-04-22 20:46:16 +01:00
Lioncash
11005cfe26
A64: Implement SLI (vector)
2020-04-22 20:46:16 +01:00
Lioncash
e3d9bf55e7
A64: Implement SRSRA (vector)
2020-04-22 20:46:16 +01:00
Lioncash
bc6016cad7
A64: Implement SRSHR (vector)
2020-04-22 20:46:16 +01:00
MerryMage
6c9c829a08
imm: Add additional bit position checks to Imm::Bits
2020-04-22 20:46:16 +01:00
MerryMage
be907a61f7
math_util: rvalue references for std::forward
2020-04-22 20:46:16 +01:00
Lioncash
a2f8cdf0a3
A64: Implement SSUBL/SSUBL2
2020-04-22 20:46:16 +01:00
Lioncash
d456fb85c8
A64: Implement SADDL/SADDL2
2020-04-22 20:46:16 +01:00
Lioncash
5c9e7f328d
A64: Implement USUBL/USUBL2
2020-04-22 20:46:16 +01:00
Lioncash
88d70e3b8a
A64: Implement UADDL/UADDL2
2020-04-22 20:46:16 +01:00
Lioncash
4b3d70de5f
simd_shift_by_immediate: Factor out common code in shift instructions
...
Gets rid of partial duplication of the same code for instructions that only have a small behavior difference to them.
e.g. The only difference between SSHR and SSRA is that SSRA adds an accumulator before storing the result.
2020-04-22 20:46:16 +01:00
Lioncash
56803f5203
A64: Implement URSRA (vector)
2020-04-22 20:46:16 +01:00
Lioncash
8afdf4b23d
A64: Implement URSHR (vector)
2020-04-22 20:46:16 +01:00
Lioncash
16613ee066
A64: Implement RSHRN/RSHRN2
2020-04-22 20:46:15 +01:00
Lioncash
937990fd2a
A64: Implement SHRN/SHRN2
2020-04-22 20:46:15 +01:00
Lioncash
80e005e5b5
A64/translate: Amend I() to also handle u8 and u16 immediates
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This is necessary for instructions like SRSHR, and other related instructions.
2020-04-22 20:46:15 +01:00
MerryMage
7969871aa3
A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated
2020-04-22 20:46:15 +01:00
MerryMage
5c95e28ed0
A64: Implement ZIP2
2020-04-22 20:46:15 +01:00
MerryMage
871aefb9a0
decoder/a64: Tweak ordering algorithm
...
Ensuring only instruction families are sorted with each other in
the fashion previously devised does not admit a total ordering.
2020-04-22 20:46:15 +01:00
MerryMage
575590d18d
ir_emitter: Remove overloads
...
Having overloads made explicit casting necesssary for these functions when
using types like UAny.
2020-04-22 20:46:15 +01:00
Lioncash
83ff7a43d1
A64: Implement RBIT (vector)
2020-04-22 20:46:15 +01:00
Lioncash
64b1f2d468
ir: Add opcode for reversing bits in a vector
2020-04-22 20:46:15 +01:00
Lioncash
9de60b60bb
A64/translate: Amend instruction prototypes erroneously marked as taking Reg
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Makes the prototypes consistent
2020-04-22 20:46:15 +01:00
Lioncash
cf81f04ed3
A64: Implement RAX1
2020-04-22 20:46:15 +01:00
Lioncash
7371e63a7b
a64_get_set_elimination_pass: Make TrackingType enum an enum class
...
Prevents placing single letter enum members into the surrounding scope.
2020-04-22 20:46:15 +01:00
Lioncash
7bcb1c115a
A64: Implement ABS (vector)
2020-04-22 20:46:15 +01:00
Lioncash
e33dcce14a
ir: Add opcodes for performing vector absolute values
2020-04-22 20:46:15 +01:00
Lioncash
84d49309b9
A64: Implement USUBW/USUBW2
2020-04-22 20:46:15 +01:00
Lioncash
e20fce6b5a
A64: Implement SSUBW/SSUBW2
2020-04-22 20:46:15 +01:00
Lioncash
00af6eeab9
A64: Implement SADDW/SADDW2
2020-04-22 20:46:15 +01:00
MerryMage
78a047f0f9
A64: Implement EXT
2020-04-22 20:46:15 +01:00
MerryMage
3472f371df
IR: Implement VectorExtract, VectorExtractLower IR instructions
2020-04-22 20:46:15 +01:00
MerryMage
8bba37089e
A64: Implement UADDW
2020-04-22 20:46:15 +01:00
MerryMage
5c47f03888
A64: Implement FMUL (vector)
2020-04-22 20:46:15 +01:00
Lioncash
a6e264c2dd
A64: Implement UABA
...
Now that we have unsigned absolute difference capabilities, we can just use this to
append onto the result via a vector add.
2020-04-22 20:46:15 +01:00
Lioncash
c2e7364d3e
A64: Implement UABD
2020-04-22 20:46:15 +01:00
Lioncash
ad5cf584ce
ir: Add opcodes for performing vector unsigned absolute differences
2020-04-22 20:46:15 +01:00
Lioncash
7780af56e3
ir_emitter: Make immediate member functions const qualified
...
These don't modify class state
2020-04-22 20:46:15 +01:00
Lioncash
701f43d61e
IR: Add opcodes for interleaving upper-order bytes/halfwords/words/doublewords
...
I should have added this when I introduced the functions for interleaving
low-order equivalents for consistency in the interface.
2020-04-22 20:46:15 +01:00
Lioncash
94f0fba16b
A64: Implement SHA1H
...
This is a fairly trivial instruction it's essentially:
result = ROL(data, 30);
2020-04-22 20:46:15 +01:00
Lioncash
3985f7bf84
emit_x64_data_processing: Deduplicate some code in zero-extension functions
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EmitZeroExtendByteToLong() can be implemented in terms of EmitZeroExtendByteToWord() and
EmitZeroExtendHalfToLong() can be implemented in terms of EmitZeroExtendHalfToWord().
2020-04-22 20:46:15 +01:00
Lioncash
40ec25356b
A64: NOP immediate variant of PRFM
...
Makes behavior identical to the literal variant of PRFM. Given this is simply a hint instruction,
this is valid behavior. The upside is that we don't fall back to Unicorn unnecessarily whenever
the instruction is encountered.
2020-04-22 20:46:15 +01:00
MerryMage
e7b60189b3
abi: Missing includes'
2020-04-22 20:46:15 +01:00
MerryMage
cdc5c3ad95
emit_x64_floating_point: Near jump instead of short jump in FPMinNumberic{32,64}
2020-04-22 20:46:15 +01:00
Lioncash
73b9e4b276
A64: system: Use an enum class for MRS/MSR register encodings
...
Reduces the need to manually write out the register bit encodings repeatedly.
2020-04-22 20:46:15 +01:00
MerryMage
df4ee0f51e
emit_X64_floating_point: Near jmp to end instead of short jmp
...
Jump destination can be further than what can be reached in a short
jump under some FPCR options.
2020-04-22 20:46:15 +01:00
Lioncash
b8d5765f9b
emit_x64_vector: Fix typo in VectorShuffleImpl
...
This is supposed to be pshufd, not pshufw (which only allows a 64-bit operand)
2020-04-22 20:46:15 +01:00
Lioncash
586b00d11d
A64: Implement REV64
2020-04-22 20:46:15 +01:00
Lioncash
ade595e377
bit_util: Do nothing in RotateRight if the rotation amount is zero
...
Without this sanitizing it's possible to perform a shift with a shift
amount that's the same size as the type being shifted. This actually
occurs when decoding ORR variants.
We could get fancier here and make this branchless, but we don't
really use RotateRight in any performance intensive areas.
2020-04-22 20:46:15 +01:00
Lioncash
9128988dc3
A64: Implement REV32 (vector)
2020-04-22 20:46:15 +01:00
Lioncash
6b0010c940
ir: Add IR opcodes for emitting vector shuffles
...
This uses the ARM terminology for sizes (Halfword -> 2 bytes, Word -> 4 bytes)
as opposed to the x86 terminology of (Word -> 2 bytes, Double word -> 4 bytes)
2020-04-22 20:46:15 +01:00
Lioncash
eb2d28d2b1
emit_x64_vector_floating_point: Fix out of bounds array access in EmitVectorOperation64
2020-04-22 20:46:15 +01:00
Lioncash
6ad1bce5e0
A64: Implement REV16 (vector)
2020-04-22 20:46:15 +01:00
Lioncash
6177c2c63d
CMakeLists: Add fp_util, macro_util and math_util headers
...
Allows the headers to show up within IDEs
2020-04-22 20:46:15 +01:00
Lioncash
7a66224d9a
A64: Implement EOR3 and BCAX
2020-04-22 20:46:15 +01:00